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US 9,520,447 B2Granted
Memory cells having a common gate terminal
AssigneeMicron Technology, Inc.
InventorsRajesh N. Gupta, Farid Nemati
Life of this patent
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Abstract
Arrays of memory cells having a common gate terminal and methods of operating and forming the same are described herein. As an example, an array of memory cells may include a group of memory cells each having a resistive storage element coupled to a select device. Each select device includes a first terminal, a second terminal, and a gate terminal, where the gate terminal is common to each memory cell of the group.
Claims17
A method of forming an array of memory cells, the method comprising:
- forming a first metal material on a substrate;
- forming a material stack on a portion of the first metal material;
- removing a portion of the material stack to form a common gate region;
- forming a first isolation material on a portion of the first metal material;
- forming a gate dielectric material on a portion of the material stack;
- forming a common gate conductive material in a portion of the common gate region, wherein the common gate conductive material is common to each of the cells of the array of memory cells;
- forming a dielectric material on the common gate conductive material;
- and
- forming a second metal material on a portion of the material stack.
6 more elements
A method of forming an array of memory cells, the method comprising:
- forming a first doped semiconductor material on a portion of a first metal material;
- forming a material stack on a portion of the first doped semiconductor material, wherein the material stack includes a first isolation material, a common gate conductive material, and a second isolation material, wherein the common gate conductive material is common to each of the memory cells of the array;
- removing a portion of the material stack;
- forming a gate dielectric material on a portion of the common gate conductive material;
- forming a base semiconductor material on a portion of the gate dielectric material;
- forming a second doped semiconductor material on a portion of the base semiconductor material;
- and
- forming a resistive storage element on a portion of the second doped semiconductor material.
5 more elements
A method of forming a device, the method comprising:
- forming a first array including a first group of memory cells, each including a resistive storage element coupled to a select device, wherein the group includes at least three memory cells such that at least two of the three memory cells are physically connected to a first sense line and at least two of the three memory cells are physically connected to a first access line;
- wherein each select device includes a base semiconductor material, a first terminal, a second terminal, and a first group gate terminal;
- and
- wherein the first group gate terminal of each select device is common to each memory cell of the first group and is common to each of the cells of the first array of memory cells.
1 more element
Dependencies are inferred from the claim text.