US 9,520,446 B2 · Innovative approach of 4F2 driver formation for high-density RRAM and MRAM

Abstract

Some embodiments of the present disclosure relate to a memory array comprising memory cells having vertical gate-all-around (GAA) selection transistors. In some embodiments, the memory array has a source region disposed within an upper surface of a semiconductor body, and a semiconductor pillar of semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region. A gate region vertically overlies the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer. A first metal contact couples the drain region to a data storage element that stores data. The vertical GAA selection transistors provide for good performance, while decreasing the size of the selection transistor relative to a planar MOSFET, so that the selection transistors do not negatively impact the size of the memory array.

Claims19

Dependent claims

A memory array, comprising:

a shared source line comprising a source region disposed within an upper surface of a semiconductor body;
a semiconductor pillar comprising semiconductor material extending outward from the upper surface of the semiconductor body and having a channel region and an overlying drain region;
a gate region vertically overlying the source region at a position laterally separated from sidewalls of the channel region by a gate dielectric layer, wherein the drain region vertically extends to a location above the gate dielectric layer, and wherein the gate region has an upper surface at locations between adjacent shared source lines, which is below top surfaces of the adjacent shared source lines;
a first metal contact configured to couple the drain region to a data storage element configured to store data;
and
an electrically isolating material arranged onto the semiconductor body and laterally separating the shared source line from an additional shared source line, wherein the electrically isolating material has a first height that is larger than a height of the semiconductor pillar.

3 more elements

A memory array, comprising:

a plurality of semiconductor pillars extending perpendicular to an upper surface of a semiconductor body, wherein respective ones of the plurality of semiconductor pillars comprise a channel region and a drain region that is disposed over the channel region;
a shared source line that extends along the upper surface of the semiconductor body in a first direction under and between multiple channel regions within a first group of the plurality of semiconductor pillars;
a gate region extending along a second direction, perpendicular to the first direction, wherein the gate region surrounds a second group of the plurality of semiconductor pillars and has an upper surface at locations between adjacent shared source lines, which is below top surfaces of the adjacent shared source lines;
a plurality of metal contacts configured to couple the drain region to a data storage element configured to store data;
and
an electrically isolating material arranged onto the semiconductor body and laterally separating the shared source line in the second direction from additional shared source lines, wherein the electrically isolating material has an upper surface that is substantially co-planar with upper surfaces of the plurality of semiconductor pillars.

3 more elements

Dependencies are inferred from the claim text.

Innovative approach of 4F2 driver formation for high-density RRAM and MRAM

Life of this patent

Innovative approach of 4F2 driver formation for high-density RRAM and MRAM

Life of this patent

Abstract

Claims19