Three-dimensional nonvolatile memory device, semiconductor system including the same, and method of manufacturing the same
AssigneeSK hynix Inc.
InventorsTae Kyung Kim, Dae Sung Eom
Life of this patent
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Abstract
A three-dimensional nonvolatile memory device includes a first vertical channel layer and a second vertical channel layer extending from a substrate, a plurality of memory cells, first selection transistors and second selection transistors spaced apart from each other along the first vertical channel layer and the second vertical channel layer, a pad, a contact plug and a bit line in a stacked configuration over the first vertical channel layer, and a common source line formed over the second vertical channel layer.
Claims8
A method of manufacturing a three-dimensional nonvolatile memory device, the method comprising:
- depositing a plurality of interlayer insulating layers and a plurality of sacrificial layers in a stacked configuration along first vertical channel layers and second vertical channel layers, wherein the first and second vertical channel layers extend from a substrate;
- etching portions of the plurality of the interlayer insulating layers and the plurality of sacrificial layers to form a slit, wherein portions of the sacrificial layers are exposed through a sidewall of the slit;
- removing the portions of the sacrificial layers exposed by the slit to form recesses between the interlayer insulating layers;
- filling the recesses with conductive layers to form a plurality of word lines;
- forming pads having a generally island shape over the first vertical channel layers;
- forming a common source line having a generally rectangular shape over the second vertical channel layers;
- forming contact plugs over the pads;
- and
- forming a bit line over the contact plugs;
- wherein a width of the pad is greater than that of the first vertical channel layer and that of the contact plug.
A method of manufacturing a three-dimensional nonvolatile memory device, the method comprising:
- depositing a plurality of interlayer insulating layers and a plurality of sacrificial layers in a stacked configuration along first vertical channel layers and second vertical channel layers, wherein the first and second vertical channel layers extend from a substrate;
- etching portions of the plurality of the interlayer insulating layers and the plurality of sacrificial layers to form a slit, wherein portions of the sacrificial layers are exposed through a sidewall of the slit;
- removing the portions of the sacrificial layers exposed by the slit to form recesses between the interlayer insulating layers;
- forming word lines within the recesses;
- forming a lower conductive layer of a common source line over the second vertical channel layers;
- forming an insulating layer covering the lower conductive layer;
- forming pads and an upper conductive layer of the common source line passing through the insulating layer, wherein the pads are formed over the first vertical channel layers and the upper conductive layer is formed over the lower conductive layer;
- forming contact plugs over the pads;
- and
- forming a bit line over the contact plugs.
Dependencies are inferred from the claim text.