NOR structure flash memory and manufacturing method thereof

A method of manufacturing a NOR flash memory having a substrate, comprising the following steps:

• providing a gate stack structure configured to form the NOR flash memory, the gate stack structure comprising a tunneling dielectric layer, a first polysilicon layer, an inter-poly layer dielectric, a second polysilicon layer having a surface inclined at a non-zero angle relative to the first polysilicon layer, which are sequentially laminated from low to up;
• forming a mask dielectric layer on the second polysilicon layer;
• etching patternedly part of the mask dielectric layer to expose part of the second polysilicon layer which is close to a source of the NOR flash memory;
• and
• self aligning the part of second polysilicon layer exposed during the etching to form a metal silicide layer;
• wherein the entire top surface of the first polysilicon layer is horizontal relative to the substrate;
• and
• wherein a portion of the top surface of the second polysilicon layer is inclined relative to the substrate.