Including low and high-voltage CMOS devices in CMOS process
AssigneeBroadcom Corporation
InventorAkira Ito
Life of this patent
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Abstract
A device includes a substrate, a deep well, a first well, and a second well. The deep well is formed in the substrate. The first well includes a first portion formed on the deep well and a second portion formed in the substrate. The second well is formed partially on the deep well. A first separator structure is formed on the deep well to isolate the first portion of the first well from the second well, and a second separator structure is formed on the substrate to isolate the second well and a second portion of the first well.
Claims20
A device comprising:
- a substrate;
- a deep well formed in the substrate;
- a first well comprising a first portion formed on the deep well and a second portion formed in the substrate;
- a second well formed partially on the deep well;
- a first separator structure formed on the deep well and configured to isolate the first portion of the first well from the second well;
- and
- a second separator structure formed on the substrate and configured to isolate the second well and a second portion of the first well.
A device comprising:
- a substrate;
- a first well formed on the substrate;
- a second well formed on the substrate;
- a separator structure formed on the substrate and configured to isolate the first well from the second well;
- an MOS transistor formed in the second well;
- a body-tie region formed in the second well;
- and
- an optional deep Nwell,
- wherein the separator structure comprises a native semiconductor layer configured to provide an isolated hi h-voltage domain.
A method for including low and high-voltage CMOS devices in CMOS process, the method comprising:
- providing a substrate;
- forming a deep well in the substrate;
- forming a first well comprising a first portion formed on the deep well and a second portion formed in the substrate;
- forming a second well partially on the deep well;
- forming a first separator structure on the deep well, and configuring the first separator structure to isolate the first portion of the first well from the second well;
- and
- forming a second separator structure on the substrate, and configuring the second separator structure to isolate the second well and a second portion of the first well.
A method for including low and high-voltage CMOS devices in CMOS process, the method comprising:
- providing a substrate;
- forming a first well on the substrate;
- forming a second well on the substrate;
- forming a separator structure on the substrate and configuring the separator structure to isolate the first well from the second well;
- forming an MOS transistor in the second well;
- and
- forming a body-tie region in the second well and an optional deer Nwell,
- wherein the separator structure comprises a native semiconductor layer configured to provide an isolated high-voltage domain.
Dependencies are inferred from the claim text.