Field effect transistor having delay element with back gate

A device comprising:

• a first transistor having a first polarity;
• a second transistor having a second polarity;
• an input connected to the first transistor and the second transistor;
• and
• an output connected to the first transistor and the second transistor,
• the first transistor comprising:
• a first channel region comprising a semiconductor;
• a first gate and a first back gate separated by the first channel region the first back gate comprising a first back gate insulator adjacent to the first channel region and a first back gate conductor adjacent to the first back gate insulator opposite the first channel region;
• a first delay element comprising a first resistor immediately adjacent to the first back gate insulator and further extending from immediately adjacent to the first back gate conductor to the output;
• and
• a first source and a first drain separated by the first channel region,
• the second transistor comprising:
• a second channel region comprising a semiconductor;
• a second gate and a second back gate separated by the second channel region, the second back gate comprising a second back gate insulator adjacent to the second channel region and a second back gate conductor adjacent to the second back gate insulator opposite the second channel region;
• a second delay element comprising a second resistor immediately adjacent to the second back gate insulator and further extending from immediately adjacent to the second back gate conductor to the output;
• a second back gate insulator separating the second back gate from the second channel region;
• and
• a second source and a second drain separated by the second channel region,
• the first gate and the second gate are connected to the input,
• the first drain and the second drain are connected to the output,
• the first source, the first drain, the second source, and the second drain comprise conductors,
• the first delay element, the first back gate insulator, the first back gate conductor, and the first channel region comprise a first resistor-capacitor (RC) circuit, and
• the second delay element, the second back gate insulator, the second back gate conductor, and the second channel region comprise a second RC circuit.

A method comprising:

• simultaneously forming a first transistor having a first polarity and a second transistor having a second polarity, opposite the first polarity, in a process comprising:
• forming a first channel region comprising a first polarity semiconductor;
• forming a second channel region comprising a second polarity semiconductor;
• forming a first source and a first drain contacting the first channel region;
• forming a second source and a second drain contacting the second channel region;
• forming a first gate conductor adjacent the first channel region;
• forming a second gate conductor adjacent the second channel region;
• forming a first back gate insulator contacting the first channel region;
• forming a second back gate insulator contacting the second channel region;
• forming a first back gate conductor contacting the first back gate insulator, the first back gate conductor is separated from the first channel region by the first back gate insulator;
• and
• forming a second back gate conductor contacting the second back gate insulator, the second back gate conductor is separated from the second channel region by the second back gate insulator;
• forming a first delay element comprising a first resistor immediately adjacent to the first back gate insulator and the first back gate conductor;
• forming a second delay element comprising a second resistor immediately adjacent to the second back gate insulator and the second back gate conductor;
• forming an input connected to the first gate conductor and the second gate conductor;
• and
• forming an output to the first drain and the second drain, the first delay element extending from immediately adjacent to the first back gate conductor to the output and the second delay element extending from immediately adjacent to the second back gate conductor to the output.