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US 9,520,385 B1Granted
Package structure and method for forming same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsHsien-Wei Chen, Kuo-Chuan Liu
Life of this patent
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Abstract
A device comprises a bottom package comprising an interconnect structure, a molding compound layer over the interconnect structure, a semiconductor die in the molding compound layer and a solder layer embedded in the molding compound layer, wherein a top surface of the solder layer is lower than a top surface of the molding compound layer and a top package bonded on the bottom package through a joint structure formed by the solder layer and a bump of the top package.
Claims20
A method comprising:
- depositing a seed layer on a dielectric layer;
- patterning a photoresist layer over the seed layer to form an opening;
- forming a solder layer in the opening;
- forming a conductive layer over the solder layer through a plating process;
- attaching a semiconductor die on the dielectric layer;
- forming a molding compound layer over the dielectric layer to form a bottom package, wherein the semiconductor die, the conductive layer and the solder layer are embedded in the molding compound layer;
- applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;
- applying a dielectric removal process to the dielectric layer until a surface of the solder layer is exposed;
- and
- mounting a top package on the bottom package.
7 more elements
A method comprising:
- depositing a seed layer on a dielectric layer;
- patterning a photoresist layer over the seed layer to form an opening;
- forming a solder layer in the opening;
- forming a nickel layer on and in contact with the solder layer;
- plating a conductive material over the nickel layer;
- removing remaining portions of the photoresist layer;
- attaching a semiconductor die on the dielectric layer;
- forming a molding compound layer over the dielectric layer to form a bottom package;
- applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;
- removing a portion of the dielectric layer to expose a surface of the solder layer;
- and
- mounting a top package on the bottom package.
9 more elements
A method comprising:
- depositing a seed layer on a dielectric layer;
- patterning a photoresist layer over the seed layer to form a first opening and a second opening;
- forming a first solder layer in the first opening and a second solder layer in the second opening;
- plating a conductive material in the first opening and the second opening to form a first via and a second via;
- attaching a semiconductor die on the dielectric layer;
- forming a molding compound layer over the dielectric layer to form a bottom package, wherein the semiconductor die, the first via and the second via are embedded in the molding compound layer;
- applying a grinding process to the molding compound layer until a surface of the semiconductor die is exposed;
- removing portions of the dielectric layer to expose the first solder layer and the second solder layer;
- and
- mounting a top package on the bottom package, wherein bumps of the top package, the first solder layer and the second solder layer form a joint structure.
7 more elements
Dependencies are inferred from the claim text.