Wafer level package (WLP) and method for forming the same

A semiconductor device structure, comprising:

• a conductive pad formed over a chip;
• an insulating layer surrounding the chip;
• a protection layer formed over the conductive pad and the insulating layer;
• a post-passivation interconnect (PPI) structure at least formed in the protection layer, wherein the PPI structure is electrically connected to the conductive pad;
• a first moisture-resistant layer formed over the protection layer, wherein the first moisture-resistant layer comprises polyimide (PI), epoxy, solder resist (SR), silicon nitride, silicon oxide, HMDS (hexamethyldisilazane), fluorine-containing polymer or combinations thereof;
• and
• an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer.

A method for forming a semiconductor device structure, comprising:

• forming a conductive pad over a substrate;
• forming a protection layer formed over the conductive pad;
• forming a post-passivation interconnect (PPI) structure and a PPI pad in the protection layer, wherein the PPI structure is electrically connected to the conductive pad, and the PPI structure is formed on the PPI pad;
• forming a first moisture-resistant layer over the protection layer, wherein the protection layer and the first moisture-resistant layer are made of different materials;
• and
• forming an under bump metallurgy (UBM) layer in the first moisture-resistant layer.