Semiconductor device and method for forming semiconductor package having build-up interconnect structure over semiconductor die with different CTE insulating layers

A semiconductor device, comprising:

• a semiconductor die including a plurality of contact pads;
• a first insulating layer formed in contact with an active surface of the semiconductor die;
• an encapsulant deposited over a second surface of the semiconductor die opposite the active surface and in a peripheral region around the semiconductor die;
• and
• an interconnect structure formed over the encapsulant and first insulating layer, wherein the interconnect structure includes,
• (a) a second insulating layer formed in direct contact with the encapsulant and first insulating layer, wherein a coefficient of thermal expansion (CTE) of the second insulating layer is within a first range of 110-150 parts per million (ppm),
• (b) a first conductive layer formed over the second insulating layer and the plurality of contact pads,
• (c) a third insulating layer formed in direct contact with the second insulating layer and first conductive layer, wherein a CTE of the third insulating layer is within a second range of 90-110 ppm,
• (d) a second conductive layer formed over the second insulating layer and first conductive layer, and
• (e) a fourth insulating layer formed in direct contact with the third insulating layer and second conductive layer, wherein a CTE of the fourth insulating layer is within a third range of 30-90 ppm.

A semiconductor device, comprising:

• a semiconductor die including a plurality of contact pads;
• a first insulating layer formed in contact with a first surface of the semiconductor die;
• an encapsulant deposited over a second surface of the semiconductor die opposite the first surface and in a peripheral region around the semiconductor die;
• and
• an interconnect structure formed over the encapsulant and first insulating layer, wherein the interconnect structure includes,
• (a) a second insulating layer formed in direct contact with the encapsulant and the first insulating layer, wherein a coefficient of thermal expansion (CTE) of the second insulating layer is within a first range,
• (b) a first conductive layer formed over the second insulating layer and the plurality of contact pads,
• (c) a third insulating layer formed in direct contact with the second insulating layer and first conductive layer, wherein a CTE of the third insulating layer is within a second range overlapping in part and different in part with respect to the first range,
• (d) a second conductive layer formed over the second insulating layer and first conductive layer, and
• (e) a fourth insulating layer formed in direct contact with the third insulating layer and second conductive layer, wherein a CTE of the fourth insulating layer is within a third range overlapping in part and different in part with respect to the second range.

A semiconductor device, comprising:

• a semiconductor die including a plurality of contact pads;
• an encapsulant deposited over the semiconductor die opposite the first surface and in a peripheral region around the semiconductor die;
• and
• an interconnect structure formed over the encapsulant and the semiconductor die, wherein the interconnect structure includes,
• (a) a first insulating layer formed over the encapsulant and semiconductor die, wherein a coefficient of thermal expansion (CTE) of the first insulating layer is within a first range,
• (b) a first conductive layer formed over the first insulating layer and the plurality of contact pads,
• (c) a second insulating layer formed in direct contact with the first insulating layer and first conductive layer, wherein a CTE of the second insulating layer is within a second range overlapping in part and different in part with respect to the first range,
• (d) a second conductive layer formed over the second insulating layer and first conductive layer, and
• (e) a third insulating layer formed in direct contact with the second insulating layer and second conductive layer, wherein a CTE of the third insulating layer is within a third range overlapping in part and different in part with respect to the second range.