Semiconductor device having interconnect layer that includes dielectric segments interleaved with metal components

A semiconductor device, comprising:

• a substrate;
• an interlayer dielectric (ILD) layer disposed over the substrate;
• a first interconnect layer disposed over the ILD layer, wherein the first interconnect layer contains a plurality of first dielectric segments, a plurality of first metal line components interleaving with the first dielectric segments, and a plurality of first dielectric barrier elements disposed between the first dielectric segments and the first metal line components;
• and
• a second interconnect layer disposed over the first interconnect layer, wherein the second interconnect layer contains a plurality of second dielectric segments, a plurality of second metal line components interleaving with the second dielectric segments, and a plurality of second dielectric barrier elements disposed between the second dielectric segments and the second metal line components;
• a plurality of vias disposed between a subset of the first metal line components and a subset of the second metal line components;
• and
• a plurality of third dielectric segments disposed between the first dielectric segments and the second dielectric segments, wherein the third dielectric segments and the second dielectric segments are separated by portions of the second dielectric barrier elements, wherein a first portion of each of the vias is surrounded by the second dielectric segments adjacent to the via, and a second portion of each of the vias is surrounded by the third dielectric segments adjacent to the via.

A semiconductor device, comprising:

• a layer containing a plurality of conductive barrier segments interdigitated with a plurality of etching-stop segments;
• a plurality of first dielectric segments disposed over the etching-stop segments, respectively;
• a plurality of conductive liner segments disposed over the conductive barrier segments, respectively, wherein portions of the conductive liner segments are disposed along sidewalls of adjacent first dielectric segments;
• a plurality of dielectric barrier segments disposed over the first dielectric segments, respectively, wherein the dielectric barrier segments contain a plurality of openings, and wherein each dielectric barrier segment of at least a subset of the plurality of the dielectric barrier segments has a sidewall that is partially contiguous with a sidewall of an adjacent conductive liner segment;
• a plurality of second dielectric segments filling the openings, respectively;
• a plurality of vias disposed over bottom portions of the conductive liner segments, respectively;
• and
• a plurality of metal line components, wherein each metal line component of a first subset of the metal line components is disposed over a respective one of the vias, and each metal line component of a second subset of the metal line components is disposed over a respective one of the first dielectric segments.