Packaging substrate and package structure
AssigneeSiliconware Precision Industries Co., Ltd.
InventorsChang-Fu Lin, Chin-Tsai Yao, Ming-Chin Chuang, Ko-Cheng Liu, Fu-Tang Huang
Life of this patent
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Abstract
A packaging substrate and a package structure are provided. The packaging substrate includes a plurality of dielectric layers, two of which have a difference in thickness; and a plurality of circuit layers alternately stacked with the dielectric layers. Therefore, the package warpage encountered in the prior art is avoided.
Claims36
A packaging substrate having a first surface and a second surface opposing the first surface, wherein the first surface is a chip mounting side, and the second surface is a non-chip mounting side, comprising:
- a core layer;
- a plurality of dielectric layers, at least two of which having a difference in thickness, wherein one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and the dielectric layers are symmetrically distributed on two opposing surfaces of the core layer with the core layer as a center;
- and a plurality of circuit layers alternately stacked with the dielectric layers.
A packaging substrate having a first surface and a second surface opposing the first surface, wherein the first surface is a chip mounting side, and the second surface is a non-chip mounting side, comprising:
- a plurality of dielectric layers, at least two of which having a difference in thickness, wherein one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and wherein one of the dielectric layers that is closest to the first surface in position has a thickness greater than each of thicknesses of the others of the dielectric layers, and one of the dielectric layers that is closest to the second surface in position has a thickness less than each of thicknesses of the others of the dielectric layers;
- and a plurality of circuit layers alternately stacked with the dielectric layers.
A package structure, comprising:
- a packaging substrate having a first surface, a second surface opposing the first surface, a core layer, a plurality of dielectric layers, and a plurality of circuit layers alternately stacked with the dielectric layers, wherein at least two of the dielectric layers have a difference in thickness, one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and the dielectric layers are symmetrically distributed on two opposing surfaces of the core layer with the core layer as a center;
- and
- a chip mounted on a first surface of the packaging substrate.
A package structure, comprising:
- a packaging substrate having a first surface, a second surface opposing the first surface, a core layer, a plurality of dielectric layers, and a plurality of circuit layers alternately stacked with the dielectric layers, wherein at least two of the dielectric layers have a difference in thickness, one of the dielectric layers that is disposed on or close to the first surface in position is greater in thickness than another one of the dielectric layers that is disposed on or close to the second surface in position, and wherein one of the dielectric layers that is closest to the first surface in position has a thickness greater than each of thicknesses of the others of the dielectric layers, and one of the dielectric layers that is closest to the second surface in position has a thickness less than each of thicknesses of the others of the dielectric layers;
- and
- a chip mounted on a first surface of the packaging substrate.
Dependencies are inferred from the claim text.