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US 9,520,331 B2Granted
Adaptive patterning for panelized packaging
AssigneeDECA Technologies Inc.
InventorsChristopher M. Scanlan, Timothy L. Olson
Life of this patent
Estimating the term…
Abstract
An adaptive patterning method and system for fabricating panel based package structures is described. Misalignment for individual device units in a panel or reticulated wafer may be adjusted for by measuring the position of each individual device unit and forming a unit-specific pattern over each of the respective device units.
Claims15
A device package comprising:
- a semiconductor die unit that further comprises an outline misaligned with a device package outline;
- an encapsulant overmolding the semiconductor die unit;
- a build-up structure disposed over both the semiconductor die unit and the encapsulant, the build-up structure comprising:
- a redistribution layer (RDL) comprising a first portion aligned with the semiconductor die unit and a second portion formed as an underbump metallization (UBM) via capture pad aligned with the semiconductor die unit, wherein the first portion of the RDL is vertically offset from the semiconductor die unit,
- a first via aligned with a bond pad of the semiconductor die unit and disposed between the bond pad and the first portion of the RDL, and
- a UBM pad aligned with the device package outline, wherein the UBM via capture pad is disposed over the UBM pad, and
- a UBM via aligned with the semiconductor die unit, wherein the UBM via is disposed between the UBM pad and the UBM via capture pad so that at least a portion of the UBM via capture pad and the UBM pad are vertically offset and connected through the UBM via;
- and
- an input/output (I/O) interconnect disposed over the UBM pad, wherein the I/O interconnect is aligned with the device package outline.
6 more elements
A device package comprising:
- a semiconductor die unit comprising an outline misaligned with a device package outline;
- an encapsulant overmolding the semiconductor die unit;
- and
- a build-up structure disposed over both the semiconductor die unit and the encapsulant, the build-up structure comprising:
- a redistribution layer (RDL) comprising a first portion aligned with the semiconductor die unit and a second portion aligned with the device package outline, wherein the first portion of the RDL is vertically offset from the semiconductor die unit,
- an electrical connecting feature aligned with a bond pad of the semiconductor die unit and disposed between the bond pad and the first portion of the RDL, and
- an underbump metallization (UBM) pad disposed over the RDL and aligned with the device package outline.
4 more elements
A device package comprising:
- a semiconductor die unit misaligned with the device package;
- an encapsulant overmolding the semiconductor die unit;
- and
- a build-up structure disposed over the semiconductor die unit, the build-up structure comprising a redistribution layer (RDL) comprising a first portion aligned with a bond pad of the semiconductor die unit and a second portion aligned with the device package, wherein the first portion of the RDL is disposed over and is vertically offset from the bond pad of the semiconductor die unit by an electrical connecting feature.
1 more element
Dependencies are inferred from the claim text.