Integrated circuit comprising PMOS transistors with different voltage thresholds

A method for the manufacture of an integrated circuit incorporating first and second pMOS transistors, comprising:

• providing a substrate, an insulating layer formed on the substrate, and a silicon layer formed on at least first and second zones of the insulating layer;
• reducing a thickness of the silicon layer above the first zone of the insulating layer, such that the silicon layer in the first zone shows a smaller thickness than the silicon layer in the second zone;
• forming a first deposit of silicon—germanium on the silicon layer above the first zone of the insulating layer and a second deposit of silicon—germanium on the silicon layer above the second zone of the insulating layer;
• forming a mask covering the second deposit of silicon—germanium and exposing the first deposit of silicon—germanium;
• in the presence of said mask, condensing germanium in the first deposit to form silicon oxide on the surface of the first deposit, such that germanium is diffused into said silicon layer below the first deposit to form a layer of silicon—germanium between said silicon oxide and said first zone of the insulating layer;
• removing said formed silicon oxide, until a thickness of the formed layer of silicon—germanium is smaller than a cumulative thickness of the second deposit of silicon—germanium and the silicon layer above the second zone of the insulating layer, such that an average density of germanium in the thickness of the silicon—germanium layer formed from the second deposit is greater than an average density of germanium in the cumulative thickness of the second deposit of silicon—germanium and the silicon layer above the second zone;
• removing said formed mask;
• and
• forming, on said silicon—germanium layer, a first gate stack of the first pMOS transistor, said first gate stack incorporating a first gate oxide and forming, on said second deposit formed on the silicon layer, a second gate stack of the second pMOS transistor, said second stack incorporating a second gate oxide, wherein the second gate oxide has a second equivalent oxide thickness, which is greater than a first equivalent oxide thickness of the first gate oxide.