Methods of forming low resistance contacts

A method for forming electrical contacts, the method comprising:

• forming a PMOS field effect transistor (FET) adjacent to an NMOS FET over a semiconductor substrate;
• forming a dielectric layer over the semiconductor substrate;
• etching contact trenches in the dielectric layer that extend to i) source and drain regions of the PMOS FET, and ii) source and drain regions of the NMOS FET;
• forming a hard mask including a first portion formed over the PMOS FET and a second portion formed over the NMOS FET;
• patterning the hard mask to remove the first portion of the hard mask;
• forming first silicide layers over the source and drain regions of the PMOS FET, wherein the second portion of the hard mask prevents the first silicide layers from forming over the source and drain regions of the NMOS FET;
• removing the second portion of the hard mask;
• forming second silicide layers over the source and drain regions of the NMOS FET;
• and
• depositing a metal layer within the contact trenches to fill the contact trenches.

A method for forming electrical contacts, the method comprising:

• forming first and second field effect transistors (FETs) over a semiconductor substrate;
• forming a dielectric layer with openings extend to i) source and drain regions of the first FET, and ii) source and drain regions of the second FET over the semiconductor substrate;
• forming a hard mask over the source and drain regions of the first and second FETs;
• removing a first portion of the hard mask, wherein the first portion is formed over the source and drain regions of the first FET;
• forming first silicide layers over the source and drain regions of the first FET, wherein the first silicide layers are formed by depositing a first metal layer over the source and drain regions of the first FET, and annealing the first metal layer to cause the first metal layer to react and form the first silicide layers;
• removing a second portion of the hard mask, wherein the second portion is formed over the source and drain regions of the second FET;
• forming second silicide layers over the source and drain regions of the second FET, wherein the second silicide layers are formed by depositing a second metal layer over the source and drain regions of the second FET, and annealing the second metal layer to cause the second metal layer to react and form the second silicide layers;
• and
• depositing a third metal layer within the openings to fill the openings.