Microelectronic packages having trench vias and methods for the manufacture thereof

A method for fabricating a microelectronic package, comprising:

• depositing a dielectric layer over a first microelectronic device including a row of contact pads, the dielectric layer covering the row of contact pads;
• forming a trench via in the dielectric layer exposing the plurality of contact pads therethrough, the trench via formed to include opposing crenulated sidewalls having a plurality of recesses adjacent to alternating contact pads in the row of contact pads;
• sputter etching the plurality of contact pads exposed through the trench via;
• and
• forming a plurality of interconnect lines over the dielectric layer each electrically coupled to the plurality of contact pads, the plurality of interconnect lines formed such that a different one of the plurality of interconnect lines extends across each of the plurality of recesses included in at least one of the opposing crenulated sidewalls.

A method for fabricating a microelectronic package, comprising:

• depositing a dielectric layer over a microelectronic device having a plurality of contact pads, the dielectric layer covering the plurality of contact pads;
• forming a crenulated trench via in the dielectric layer exposing the plurality of contact pads therethrough, the crenulated trench via comprising alternating narrow and wide sections, the narrow sections comprising elongated fingers substantially aligned with the plurality of contact pads and having inner terminal ends terminating adjacent the plurality of contact pads;
• sputter etching the plurality of contact pads exposed through the crenulated trench via;
• and
• producing interconnect lines over the dielectric layer and extending into the crenulated trench via to electrically contact the plurality of contact pads.