Integrated circuits and methods for fabricating integrated circuits with self-aligned vias

A method for fabricating an integrated circuit, the method comprising:

• forming a first interconnect line overlying a semiconductor substrate;
• forming an insulator cap defining a gap overlying the first interconnect line;
• depositing a dielectric over the insulator cap and the first interconnect line;
• forming a first mask over the dielectric and having an opening exposing a first region of the dielectric;
• forming a second mask over the first mask and the dielectric and exposing a second region of the dielectric within the first region and directly overlying the gap;
• etching the second region to form a recess in the first region;
• removing the second mask;
• etching the first region to convert the recess to a via extending into the gap to expose the first interconnect line and to form a trench located above the via;
• and
• depositing a conductive material into the trench and the via to form a second interconnect line and a conductive via in contact with the first interconnect line.

A method for fabricating an integrated circuit, the method comprising:

• forming an insulator cap over a semiconductor substrate and defining a gap;
• depositing a barrier layer over the semiconductor and in the gap;
• depositing a first conductive material over the barrier layer and in the gap;
• recessing the first conductive material;
• removing an exposed portion of the barrier liner;
• depositing a second conductive material over the first conductive material to form a conductive interconnect line;
• depositing an upper interlayer dielectric material over the insulator cap and over the conductive interconnect line;
• etching a via through the upper interlayer dielectric material to expose the conductive interconnect line;
• and
• depositing a third conductive material into the via to form a conductive via in contact with the conductive interconnect line.