US 9,520,296 B2 · Semiconductor device having a low divot of alignment between a substrate and an isolation thereof and method of forming the same

Abstract

According to an exemplary embodiment, a method of forming vertical structures is provided. The method includes the following operations: providing a substrate; forming a first oxide layer over the substrate; forming a first dummy layer over the first oxide layer; etching the first oxide layer and the first dummy layer to form a recess; forming a second dummy layer in the recess (and further performing CMP on the second dummy layer and stop on the first dummy layer); removing the first dummy layer; removing the first oxide layer; and etching the substrate to form the vertical structure. According to an exemplary embodiment, a semiconductor device is provided. The semiconductor device includes: a substrate; an STI embedded in the substrate; and a vertical transistor having a source substantially aligned with the STI.

Claims17

Dependent claims

A method of forming vertical structures, comprising:

providing a substrate;
forming a first oxide layer over the substrate;
forming a shallow trench isolation to divide the substrate into a first region and a second region;
forming a first dummy layer over the first oxide layer and the shallow trench isolation;
etching the first oxide layer and the first dummy layer to form a first recess in the first region and a second recess in the second region;
forming a second dummy layer in the first recess and the second recess;
removing the first dummy layer;
removing the first oxide layer;
etching a portion of the shallow trench isolation;
and
etching the substrate to make the substrate aligned with a top of the shallow trench isolation and to form a first vertical structure in the first region and a second vertical structure in the second region.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application

14/302,568Filed 12 Jun 2014

Published

US 2015/0364333 A117 Dec 2015

Granted

13 Dec 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification10 codes

H10P 50/694
Characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane: characterised by their behaviour…
H10D 30/025
Of FETs having insulated gates [IGFET]: of vertical IGFETs
H10D 30/63
Insulated-gate field-effect transistors [IGFET]: vertical IGFETs
H10D 62/116
Dielectric isolations, e.g. air gaps: adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions

Semiconductor device having a low divot of alignment between a substrate and an isolation thereof and method of forming the same

Life of this patent

Semiconductor device having a low divot of alignment between a substrate and an isolation thereof and method of forming the same

Life of this patent

Abstract

Claims17