Aging-based leakage energy reduction method and system
AssigneeEmpire Technology Development LLC
InventorMiodrag Potkonjak
Life of this patent
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Abstract
A technique of reducing leakage energy associated with a post-silicon target circuit is generally described herein. One example method includes purposefully aging a plurality of gates in the target circuit based on a targeted metric including a timing constraint associated with the target circuit.
Claims34
A method to reduce leakage energy associated with a post-silicon target circuit, the method comprising:
- selecting a plurality of gates in the target circuit to be aged;
- determining an extent to which to age the selected plurality of gates;
- identifying a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;
- based on the targeted metric, aging, to the determined extent, the first set of gates;
- and
- based on the targeted metric, aging, to less than the determined extent, the second set of gates.
A non-transitory computer-readable medium that includes instructions to reduce leakage energy associated with a post-silicon target circuit, which in response to execution by a processor, cause the processor to perform or control performance of:
- select a plurality of gates in the target circuit to be aged;
- determine an extent to which to age the selected plurality of gates;
- identify a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;
- based on the targeted metric, age, to the determined extent, the first set of gates;
- and
- based on the targeted metric, age, to less than the determined extent, the second set of gates.
A computing device coupled to a post-silicon target circuit and configured to reduce leakage energy associated with the post-silicon target circuit, comprising:
- a programmable unit;
- and
- a processor, coupled to the programmable unit, wherein the processor is configured to:
- select a plurality of gates in the target circuit to be aged;
- determine an extent to which to age the selected plurality of gates;
- identify a first set of gates and a second set of gates of the selected plurality of gates that will be aged differently based on a targeted metric including a timing constraint associated with the target circuit;
- based on the targeted metric, age, to the determined extent, the first set of gates;
- and
- based on the targeted metric, age, to less than the determined extent, the second set of gates.
Dependencies are inferred from the claim text.