Semiconductor memory device for performing both of static test and dynamic test during wafer burn-in test and method for operating the same

Abstract

A semiconductor memory device includes a first address input block which receives first information applied from an exterior as a corresponding normal address in a normal mode and receives the first information as a test clock in a test mode, a second address input block which receives second information applied from an exterior as the corresponding normal address in the normal mode and receives the second information as a test code in the test mode, and a test signal generation block which synchronizes the test code with the test clock in the test mode and generates a test command, a test address and a test data in response to a synchronized test code.

Dependencies are inferred from the claim text.