Nonvolatile memory device comprising page buffer and program verification operation method thereof

A nonvolatile memory device, comprising:

• a cell array including a plurality of memory cells;
• a first page buffer configured to connect to a first bit line of a first memory cell of the plurality of memory cells, the first page buffer including a first A latch configured to store first upper bit data and a first B latch configured to store first lower bit data;
• a second page buffer configured to connect to a second bit line of a second memory cell of the plurality of memory cells, the second page buffer including a second A latch configured to store second upper bit data and a second B latch configured to store second lower bit data;
• and
• a control logic configured to apply a set pulse to both the first A latch and the second B latch, or to both the second A latch and the first B latch, to set the first and second page buffers to be in a program inhibit state.

A method of operating a nonvolatile memory device including a first page buffer having a first sensing latch, a first sensing node, and a first data latch, and a second page buffer having a second sensing latch, a second sensing node, and a second data latch, the operating method comprising:

• developing the first and second sensing nodes according to data stored at the first and second data latches;
• setting the first data latch according to a voltage level of the first sensing node in response to a set pulse;
• and
• setting the second data latch according to a voltage level of the second sensing node in response to the set pulse.