Sensing amplifier utilizing bit line clamping devices and sensing method thereof

A sensing method, for sensing data stored in a memory cell of a memory string of which one end is coupled to a third node and another end is coupled to a common source line, the sensing method comprising:

• providing a sensing amplifier comprising a clamp circuit, the clamp circuit being coupled between a first node and a second node;
• providing a first bias signal to a control terminal of a first P-type transistor of the clamp circuit, wherein the first terminal and the second terminal of the first P-type transistor are coupled to the first and second nodes, respectively,
• providing an isolating transistor coupled between the third node and the first node;
• and
• setting the voltage level of the third node to be less than the voltage level of the common source line in a bias setup time period, and accordingly clamping, by the first P-type transistor, the voltage level of the first node to be higher than the voltage level of the second node, such that a sensing current from the memory cell flows into the second node via the first node during a sensing time period subsequent to the bias setup time period.

A sensing amplifier, for sensing data stored in a memory cell, comprising:

• a clamp circuit coupled between a first node and a second node, wherein the clamp circuit comprises a first P-type transistor having a first terminal, a second terminal and a control terminal receiving a first bias signal, the first terminal and the second terminal of the first P-type transistor are coupled to the first node and the second node, respectively;
• an isolating transistor, coupled between the first node and a third node coupled to a memory string including the memory cell;
• and
• a pre-charging and sensing circuit having a sensing capacitor, wherein one terminal of the sensing capacitor is coupled to the second node, and the other terminal of the sensing capacitor receives a clock signal, wherein the voltage level of the clock signal is pulled low during the sensing time period;
• wherein the voltage level of the third node is set to be less than the voltage level of the common source line in a bias setup time period, and the first P-type transistor accordingly clamps the voltage level of the first node to be higher than the voltage level of the second node, such that a sensing current from the memory cell flows into the second node via the first node during a sensing time period subsequent to the bias setup time period.