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US 9,520,190 B2Granted
Modified reset state for enhanced read margin of phase change memory
AssigneeMicron Technology, Inc.
InventorsMattia Boniardi, Andrea Redaelli, Fabio Pellizzer, Daniele Ielmini, Agostino Pirovano
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Abstract
Subject matter disclosed herein relates to techniques involving a structural relaxation (SR) phenomenon for increasing resistance of a Reset state of phase change memory.
Claims20
A method, comprising:
- applying a first electrical signal to a memory cell for programming the memory cell to a resistance state;
- comparing a current value of a test signal applied to the memory cell to a threshold current value;
- determining a fall time associated with a second electrical signal based at least in part on the comparing;
- and
- applying the second electrical signal to the memory cell for programming the memory cell to an increased resistance state, wherein the second electrical signal comprises an added trailing edge time relative to the first electrical signal based at least in part on the determining, and wherein the fall time of the second electrical signal is greater than a rise time of the second electrical signal.
2 more elements
A memory device, comprising:
- a memory array comprising a memory cell, wherein the memory cell comprises phase change memory;
- and
- a memory controller configured to:
- apply a first electrical signal to the memory cell for programming the memory cell to a resistance state;
- compare a current value of a test signal applied to the memory cell and a threshold current value;
- determine a fall time associated with a second electrical signal based at least in part on the comparing;
- and
- apply the second electrical signal to the memory cell for programming the memory cell to an increased resistance state, wherein the second electrical signal comprises an added trailing edge time relative to the first electrical signal based at least in part on the determining, and wherein the fall time of the second electrical signal is greater than a rise time of the second electrical signal.
5 more elements
A system, comprising:
- a memory array comprising a memory cell, wherein the memory cell comprises phase change memory;
- a memory controller configured to program the memory cell in response to a write command, wherein the memory controller is configured to program the memory cell by:
- applying a first electrical signal to the memory cell for programming the memory cell to a resistance state;
- comparing a current value of a test signal applied to the memory cell and a threshold current value;
- determining a fall time associated with a second electrical signal based at least in part on the comparing;
- and
- applying the second electrical signal to the memory cell for programming the memory cell to an increased resistance state, wherein the second electrical signal comprises an added trailing edge time relative to the first electrical signal based at least in part on the determining, and wherein the fall time of the second electrical signal is greater than a rise time of the second electrical signal;
- and
- a processor configured to initiate the write command for accessing the memory array.
6 more elements
Dependencies are inferred from the claim text.