Asynchronous FIFO memory with read and write counter circuitry

A read count circuit for providing a count of data read from an asynchronous FIFO memory device, the FIFO memory device providing a read clock signal, a write clock signal, a read enable signal, and a write enable signal, with each of the clock signals having an associated clock frequency, the circuit comprising:

• a shift register comprising a number of cascaded flip-flops, each flip-flop having the write clock signal as its clock input, and the data output of the preceding flip-flop as its data input, with the data output of the last flip-flop being the data input to the first flip-flop;
• wherein the number of flip-flops is the size of a data vector whose size is based on a ratio of one clock frequency to the other;
• an AND element at the output of each flip-flop, operable to AND the output of the associated flip-flop with the write enable signal;
• a pulse generator at the output of each AND element, operable to synchronize the outputs of the AND elements with the read clock;
• an adder operable to receive and sum the outputs of each pulse generator, thereby providing a write pulse sum;
• and
• a counter operable to increment with the write pulse sum and to decrement with the read enable signal upon each read clock signal, thereby providing a read count output.