Semiconductor device having hierarchical sense amplifiers assigned to multiple local bit lines

A semiconductor device comprising:

• a global bit line;
• a global sense amplifier which amplifies a signal on the global bit line;
• first and second local bit lines;
• a plurality of word lines which each intersect both the first and second local bit lines;
• a plurality of memory cells disposed at the points of intersection of the plurality of word lines and the first and second local bit lines;
• first and second hierarchical switches connected respectively between the first and second local bit lines and the global bit line;
• an amplification circuit which has a first signal node and which amplifies a signal supplied to the first signal node to either a first level or a second level;
• a first selection transistor provided between the first signal node and the first local bit line;
• and
• a second selection transistor provided between the first signal node and the second local bit line.