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US 9,520,176 B2Granted
Semiconductor memory device including power supply line
AssigneeMicron Technology, Inc.
InventorMinoru Yamagami
Life of this patent
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Abstract
A semiconductor apparatus disclosed in this disclosure includes a first channel formed in a first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array; a second channel formed in a second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other; and mesh structure lines straddling the first area and second area and connected to the first and second power supply pads.
Claims12
A semiconductor apparatus comprising:
- a plurality of first pads including a first power supply pad and a first data input/output pad, the plurality of first pads aligned to a first line elongated in a first direction;
- a plurality of second pads including a second power supply pad and a second data input/output pad, the plurality of second pads aligned to a second line elongated in the first direction;
- first and second memory cell arrays arranged between the plurality of first pads and the plurality of second pads in a second direction crossing the first direction;
- a first main amplifier arranged between the first memory cell array and the plurality of first pads;
- a second main amplifier arranged between the second memory cell array and the plurality of second pads;
- a first data input/output circuit coupled between the first data input/output pad and the first main amplifier;
- a second data input/output circuit coupled between the second data input/output pad and the second main amplifier;
- a first signal line coupled between the first main amplifier and the first data input/output circuit;
- a second signal line coupled between the second main amplifier and the second data input/output circuit;
- a primary power supply line arranged between the first and second main amplifiers;
- wherein the first signal line extends along the second direction from an edge of the primary power supply line, and is sandwiched between a pair of shielding power supply lines that extend in the second direction along opposing surfaces of the first signal line;
- wherein a width of the primary power supply line is wider than a width of the first signal line;
- and
- wherein the shielding power supply lines are about the same width as the first signal line.
11 more elements
A semiconductor apparatus including a first area and a second area, comprising:
- a first channel formed in the first area and including a first power supply pad, a first clock pad, a first command address pad, a first data input/output pad and a first memory cell array;
- a second channel formed in the second area and including a second power supply pad, a second clock pad, a second command address pad, a second data input/output pad and a second memory cell array, the first and second channels being independently controllable from each other;
- mesh structure lines straddling the first area and second area and connected to the first and second power supply pads;
- wherein the first channel includes a first main input/output line connected between a first data input/output circuit coupled to the first data input/output pad and a first main amplifier coupled to the first memory cell array, and the second channel includes a second main input/output line connected between a second data input/output circuit coupled to the second data input/output pad and a second main amplifier coupled to the second memory cell array;
- and
- wherein a width of the first and second input/output lines is narrower than that of the mesh structure lines.
3 more elements
A semiconductor apparatus comprising:
- a plurality of first pads including a first power supply pad and a first data input/output pad, the plurality of first pads aligned to a first line elongated in a first direction;
- a plurality of second pads including a second power supply pad and a second data input/output pad, the plurality of second pads aligned to a second line elongated in the first direction;
- first and second memory cell arrays arranged between the plurality of first pads and the plurality of second pads in a second direction crossing the first direction;
- a first main amplifier arranged between the first memory cell array and the plurality of first pads;
- a second main amplifier arranged between the second memory cell array and the plurality of second pads;
- a first data input/output circuit coupled between the first data input/output pad and the first main amplifier;
- a second data input/output circuit coupled between the second data input/output pad and the second main amplifier;
- a first signal line coupled between the first main amplifier and the first data input/output circuit;
- a second signal line coupled between the second main amplifier and the second data input/output circuit;
- and
- a primary power supply line arranged between the first and second main amplifiers;
- wherein the first signal line extends along the second direction from an edge of the primary power supply line, and is sandwiched between a pair of shielding power supply lines that extend in the second direction along opposing surfaces of the first signal line;
- and
- wherein a width of the primary power supply line is wider than a width of the first signal line.
11 more elements
Dependencies are inferred from the claim text.