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US 9,520,173 B1Granted
Magnetic random access memory (MRAM) and method of operation
AssigneeFreescale Semiconductor, Inc.
InventorsFrank K. Baker, Jr., Michael A. Sadd, Anirban Roy, Bruce L. Morton
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Abstract
A memory device includes a first memory cell having a first transistor, a second transistor, and a resistive storage element. During a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element. During a write operation, current is conducted through the first and second transistors.
Claims20
A memory device comprising:
- a first memory cell including a first transistor, a second transistor, and a resistive storage element, wherein
- during a read operation, sense current is conducted through the second transistor and the first transistor is used to sense feedback voltage at a first terminal of the resistive storage element, and
- during a write operation, current is conducted through the first and second transistors.
A method of operating a memory device comprising:
- providing a sense current through a first transistor of a first memory cell;
- sensing a first feedback voltage at a first current electrode of a second transistor in the first memory cell, wherein the first feedback voltage is at a first terminal of a resistive storage element and the first current electrode of the second transistor of the first memory cell is coupled to an input of a sense amplifier;
- sensing a second feedback voltage at a first current electrode of a first transistor of a second memory cell, wherein the second feedback voltage is at a second terminal of the resistive storage element and the first current electrode of the first transistor of the second memory cell is coupled to another input of the sense amplifier;
- adjusting the sense current through the first memory cell based on the first and second feedback voltages.
1 more element
An integrated circuit device comprising:
- a memory device including:
- a first memory cell having a first transistor, a second transistor, and a non-volatile programmable resistor;
- a bit line coupled to a first current electrode of the first transistor during a read operation;
- a sense amplifier including an input coupled to a first current electrode of the second transistor during the read operation;
- a write voltage coupled to the first current electrode of the first and second transistors during a write operation;
- a second current electrode of the first and second transistors coupled to a first terminal of the non-volatile programmable resistor;
- a source line coupled to a second terminal of the non-volatile programmable resistor;
- a word line coupled to a control electrode of the first and second transistors.
5 more elements
Dependencies are inferred from the claim text.