US 9,520,169 B2 · Semiconductor device

Abstract

One semiconductor device includes a clock signal buffer circuit which, in response to activation of a chip selection signal (CS_n), starts generation of an internal clock signal PCLKAR, and internal circuits which operate in synchronization with the internal clock signal PCLKAR. The clock signal buffer circuit suspends generation of the internal clock signal PCLKAR at a second timing if command signals (CA0 to CA9) indicate read commands, and suspends generation of the internal clock signal PCLKAR at a first timing which is earlier than the second timing if the command signals (CA0 to CA9) indicate active commands. According to one embodiment, an internal clock signal is generated only for periods necessary in accordance with external command signals.

Claims14

Dependent claims

A semiconductor device comprising:

a first circuit for generating a second clock signal in accordance with a first clock signal;
a second circuit for generating an internal command signal synchronous with the second clock signal in accordance with an external command signal input synchronously with the first clock signal;
and
a third circuit for activating the first circuit throughout a predetermined period corresponding to the first period, in accordance with a chip select signal input synchronously with the first clock signal;
wherein, when the external command signal exhibits a first value, the first circuit stops the second clock signal in response to a first period having elapsed from input of the external command signal, and when the external command signal exhibits a second value different than the first value, the first circuit stops the second clock signal in response to a second period longer than the first period having elapsed from input of the external command signal.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor device

Life of this patent

Semiconductor device

Life of this patent

Abstract

Claims14