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US 9,520,165 B1Granted
High-speed pseudo-dual-port memory with separate precharge controls
AssigneeQUALCOMM Incorporated
InventorsNishith Nitin Desai, Tony Chung Yiu Kwok, Changho Jung
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Abstract
A pseudo-dual-port (PDP) memory such as a PDP SRAM is provided that independently controls the bit line precharging and the sense amplifier precharging to increase memory operating speed while eliminating or reducing the discharge of crowbar current.
Claims20
A pseudo-dual-port (PDP) memory, comprising:
- a pair of bit lines;
- a bit line precharge circuit configured to precharge the pair of bit lines responsive to an assertion of a bit line precharge signal;
- a read multiplexer configured to selectively couple the pair of bit lines to a pair of input nodes of a sense amplifier responsive to an assertion of a read multiplexer signal;
- a sense amplifier precharge circuit for precharging the pair of input nodes of the sense amplifier responsive to an assertion of a sense amplifier precharge signal;
- and
- a control signal generator configured to assert the bit line precharge signal responsive to a self-timed falling edge of a first memory clock that occurs while a sense enable signal is asserted during a read operation in a first portion of a system clock cycle and to assert the sense amplifier precharge signal responsive to a falling edge of the sense enable signal to precharge the pair of input nodes for the sense amplifier prior to a write operation in a second portion of the system clock cycle.
3 more elements
A method, comprising:
- coupling a pair of bit lines to a corresponding pair of input nodes for a sense amplifier during a read operation in a first portion of a system clock cycle for a pseudo-dual-port memory to develop a voltage difference across the input nodes;
- asserting a sense enable signal for a sense amplifier assertion period during the read operation to cause the sense amplifier to sense the voltage difference;
- during the sense amplifier assertion period in the read operation, precharging the bit lines while isolating the pair of bit lines from the pair of input nodes;
- after a completion of the sense amplifier enable assertion period, precharging the pair of input nodes while isolating the pair of bit lines from the pair of input nodes for a write operation in a second portion of the system clock cycle for the pseudo-dual-port memory.
1 more element
A pseudo-dual-port (PDP) memory, comprising:
- a pair of bit lines;
- a bit line precharge circuit configured to precharge the pair of bit lines responsive to an assertion of a bit line precharge signal;
- a read multiplexer configured to selectively couple the pair of bit lines to a corresponding pair of input nodes of a sense amplifier responsive to an assertion of a read multiplexer signal;
- a sense amplifier precharge circuit for precharging the pair of input nodes of the sense amplifier responsive to an assertion of a sense amplifier precharge signal;
- first means for asserting the bit line precharge signal responsive to a delayed version of a falling edge of a memory clock for a read operation during a first portion of a system clock cycle and for de-asserting the bit line precharge signal responsive to a delayed version of a rising edge of the memory clock;
- and
- second means for asserting the sense amplifier precharge signal responsive to a delayed version of a falling edge for a sense enable signal to precharge the pair of input nodes for the sense amplifier prior to a write operation in a second portion of the system clock cycle.
4 more elements
Dependencies are inferred from the claim text.