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US 9,520,164 B1Granted
ZQ calibration circuit and semiconductor device including the same
AssigneeKabushiki Kaisha Toshiba
InventorsKensuke Yamamoto, Kosuke Yanagidaira, Shouichi Ozaki
Life of this patent
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Abstract
According to one embodiment, a ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.
Claims16
A ZQ calibration circuit, comprising:
- a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.
A ZQ calibration circuit, comprising:
- a plurality of replica buffer circuits having a circuit configuration substantially identical to a circuit configuration of an output buffer circuit and to which different electric stresses are pre-applied;
- and
- a selection circuit configured to select one of the plurality of replica buffer circuits according to a usage status of the output buffer circuit.
A semiconductor device, comprising:
- a ZQ calibration circuit, wherein
- the ZQ calibration circuit comprises a replica buffer controller configured to apply electric stress to a replica buffer circuit with a circuit configuration substantially identical to a circuit configuration of an output buffer circuit according to a usage status of the output buffer circuit during a period when no calibration operation is performed.
Dependencies are inferred from the claim text.