Hash generation circuitry and methods for multi-channel, multi-lane encryption and authentication
AssigneeAltera Corporation
InventorMartin Langhammer
Life of this patent
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Abstract
Encryption/authentication circuitry includes an authentication portion operating on a plurality of lanes of encrypted data spanning a number of channels, and including hash constant storage for a predetermined maximum number of channels, and partial hash selection circuitry for determining, for each respective lane, a respective hash index into the hash constant storage. Wind-down mode detection circuitry also is described, as well as a method of operating such circuitry also is provided.
Claims24
Encryption and authentication circuitry comprising:
- an encryption circuit outputting at least one lane of encrypted data spanning a number of channels;
- and
- an authentication circuit operating on said at least one lane of encrypted data spanning said number of channels, said authentication circuit including:
- hash constant storage for a predetermined maximum number of channels,
- partial hash selection circuitry for determining, for each respective lane, a respective hash index into said hash constant storage, and
- an adder for adding, to data in said at least one lane of encrypted data, a hash constant selected from said hash constant storage using said respective hash index.
A method of tracking partial hash states during encryption and authentication of a plurality of channels of data using circuitry having at least one authentication lane, said method comprising, for each respective one of said channels, determining a hash index by:
- storing an initialized index in memory in said circuitry;
- and
- for each respective lane of said circuitry:
- comparing a channel number in data in said respective lane of said circuitry to a channel number of said respective one of said channels, and
- adding output of the comparison in said respective lane of said circuitry (1) to said initialized index when said respective lane is a first one of said lanes of said circuitry, or (2) to output of another of said adding in another one of said lanes of said circuitry when said respective lane is other than a first one of said lanes.
Dependencies are inferred from the claim text.