Domain-specific hardwired symbolic machine that validates and maps a symbol

An apparatus, comprising:

• a plurality of memory blocks configured to store symbols of textual data;
• first circuitry configured as a plurality of domains that define valid textual data values of the symbols, wherein the plurality of domains is hardwired into the apparatus;
• second circuitry configured as a first pipe segment, wherein the first pipe segment includes combinatorial logic and is configured to, via its combinatorial logic, receive a symbol for mapping from a first memory block, validate that the textual data of the symbol for validating is valid according to one of the plurality of domains to generate a validated symbol, and output the validated symbol to a second memory block;
• and
• third circuitry configured as a second pipe segment, wherein the second pipe segment includes combinatorial logic and is configured to, via its combinatorial logic, receive a symbol for mapping from the second memory block, map the textual data of the symbol for mapping from a first of the plurality of domains to a second of the plurality of domains to generate a mapped symbol, and output the mapped symbol to a third memory block.

A method comprising:

• receiving a definition of a function of an application to be implemented in an apparatus;
• determining a list of domains, a list of variable objects and a list of maps based on the definition;
• determining, based on the list of domains, domain validation pipe circuitry to produce a plurality of domain validation pipe circuits that are each configured to validate input as having a valid value according to at least one domain in the list of domains;
• determining, based on the list of maps, domain manning pipe circuitry to produce a plurality of domain mapping pipe circuits that are each configured to man input between a first domain in the list of domains to a second domain in the list of domains;
• determining, based on the list of variable objects, memory block circuitry to produce a plurality of memory block circuits, the plurality of memory block circuits being configured to (a) provide input to and receive output from the plurality of domain validation pipe circuits and (b) provide input to and receive output from the plurality of domain mapping pipe circuits;
• and
• implementing the plurality of domain validation pipe circuits, the plurality of domain mapping pipe circuits and the plurality of memory block circuits into the apparatus such that the apparatus is capable of performing the function.