Returning to a control transfer instruction
AssigneeIntel Corporation
InventorsBaiju Patel, Vedvyas Shanbhogue, Ravi Sahita
Life of this patent
Estimating the term…
Abstract
In an embodiment, the present invention includes a processor having a decode unit and an execution unit. The decode unit is to decode control transfer instructions and the execution unit is to execute control transfer instructions, the control transfer instructions including a call instruction and a return instruction. The processor is to operate in a first mode in which the processor is to raise a fault if a next instruction to be executed immediately after the return instruction is not the call instruction.
Claims14
A processor to operate in a first mode and a second mode, comprising:
- front-end hardware including:
- a decoder to decode a plurality of control transfer instructions, the plurality of control transfer instructions including a call instruction and a return instruction;
- and
- a state machine to raise a fault in the first mode if a next instruction to be executed immediately after the return instruction is not the call instruction;
- wherein, in the first mode, execution of the call instruction is to include pushing on a stack an address of the call instruction, and
- wherein, in the second mode, execution of the call instruction is to include pushing on the stack an address of an instruction immediately following the call instruction.
A method comprising:
- decoding, by a processor, a call instruction;
- executing, if the processor is in a first mode, the call instruction, including pushing on a stack an address of the call instruction;
- executing, if the processor is in a second mode, the call instruction, including pushing on the stack an address of an instruction immediately following the call instruction;
- decoding, by the processor, a return instruction;
- determining, by the processor in the first mode, whether a next instruction immediately after the return instruction is not a call instruction;
- and
- raising a fault in response to determining, in the first mode, that the next instruction is not a call instruction.
A system comprising:
- a memory including a sequence of instructions to be executed by a processor, the sequence of instructions including a call instruction and a return instruction;
- and
- the processor, including
- a decode unit to decode the sequence of instructions, and
- an execution unit to execute the sequence of instructions;
- wherein the processor is to operate in a first mode in which execution of the call instruction is to include pushing on a stack a memory address of the call instruction and in which the processor is to raise a fault if a next instruction to be executed immediately after the return instruction is not the call instruction;
- and
- wherein the processor is also to operate in a second mode in which execution of the call instruction is to include pushing on the stack a memory address of an instruction immediately following the call instruction.
Dependencies are inferred from the claim text.