Optimal stacked transistor placement to increase single event transient robustness

A method, comprising:

• receiving a description of an integrated circuit;
• determining in the description of the integrated circuit a first logic gate with a first output, a first transistor coupled to the first output, and a second transistor coupled between the first transistor and a voltage supply terminal;
• determining in the description of the integrated circuit a second logic gate with a second output that is coupled to an input of the first logic gate and a third transistor that is coupled to the second output;
• and
• generating a layout of the description of the integrated circuit, wherein the layout places the first, second, and third transistors on a substrate, and wherein a single-event transient charge injected at the second output is shared with the second transistor through the substrate.

Non-transitory computer-readable storage media for generating a layout of a circuit description, the non-transitory computer-readable storage media comprising instructions for:

• determining in the circuit description first and second gates, wherein the first gate has an output, a first transistor coupled to the output, and a second transistor coupled between the first transistor and a voltage supply terminal, and wherein the second gate has an output that is coupled to an input of the first gate;
• determining whether the output of the second gate can be placed closer to the output of the first gate than to the second transistor in the layout of the circuit description;
• and
• in response to determining that the output of the second gate cannot be placed closer to the output of the first gate than to the second transistor in the layout of the circuit description, generating a layout of the circuit description, in which the output of the second gate is placed closer to the second transistor than to the output of the first gate to reduce a single event transient duration.