Processor with instruction variable data distribution

A vector processor comprising:

• a plurality of execution units arranged in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• and
• a plurality of load units, each of the load units configured to:
• retrieve values from locations of memory via alternate memory lanes in a single transaction;
• and
• load the values to adjacent registers of the plurality of registers in a single transaction.

A vector processor comprising:

• a plurality of execution units arranged in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• and
• a plurality of load units, each of the load units configured to:
• retrieve values from locations of the memory via adjacent memory lanes in a single transaction;
• and
• load a copy of each of the values into a plurality of adjacent registers in a single transaction.

A vector processor comprising:

• a plurality of execution units arranged in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of store units, each of the store units configured to:
• retrieve a plurality of values from adjacent ones of the registers in a single transaction;
• and
• write, in a single transaction, each of the values into memory at a location offset from a location of an immediately preceding write by one more than a number of values retrieved from the registers.

A vector processor comprising:

• a plurality of execution units arranged in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of store units, each of the store units configured to:
• retrieve a plurality of values from adjacent ones of the registers in a single transaction;
• and
• write a sub-plurality of the retrieved values to locations in memory via adjacent memory lanes in a single transaction, the sub-plurality selected in accordance with a template value stored in a register of the vector processor.

A vector processor comprising:

• a plurality of execution units arranged in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of store units, each of the store units configured to:
• retrieve a plurality of values from adjacent ones of the registers in a single transaction;
• and
• write the values to alternate locations in the memory in a single transaction.

A processor comprising:

• a scalar processor core;
• and
• a vector coprocessor core coupled to the scalar processor core;
• the vector coprocessor core configured to execute vector instructions passed by the scalar processor core, the vector coprocessor core comprising:
• a plurality of execution units arranged to execute an instruction in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of load units configured to execute a load instruction specifying upsampling by a factor of two while moving a plurality of data values from memory to the registers in a single transaction;
• and
• a plurality of store units configured to execute a store instruction specifying downsampling by a factor of two while moving a plurality of data values from the registers to memory in a single transaction.

A processor comprising:

• a scalar processor core;
• and
• a vector coprocessor core coupled to the scalar processor core;
• the vector coprocessor core configured to execute vector instructions passed by the scalar processor core, the vector coprocessor core comprising:
• a plurality of execution units arranged to execute an instruction in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of load units configured to execute a load instruction specifying expansion of data stored in memory in compacted form while moving a plurality of data values from memory to the registers in a single transaction, the expansion based on a template stored in a register of the vector coprocessor core;
• and
• a plurality of store units configured to execute a store instruction specifying compaction of data stored in the registers while moving a plurality of data values from the registers to memory in a single transaction, the compaction based on a template stored in a register of the vector coprocessor core.

A processor comprising:

• a scalar processor core;
• and
• a vector coprocessor core coupled to the scalar processor core;
• the vector coprocessor core configured to execute vector instructions passed by the scalar processor core, the vector coprocessor core comprising:
• a plurality of execution units arranged to execute an instruction in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of load units configured to execute a store instruction specifying a selectable distribution that causes at least one of the store units to move values retrieved from a plurality of adjacent ones of the registers to locations in memory via alternate memory lanes in a single transaction.

A vector processor comprising:

• a plurality of execution units arranged in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• and
• a plurality of load units, at least one of the load units configured to move a predetermined number of values in adjacent memory locations to adjacent registers as controlled by expansion control information, the expansion control information having a number of bits equal to the number of registers, with a number of 1 bits equal to the predetermined number of values, a register storing all 0s if a corresponding bit of the expansion control information 0 and a next of the predetermined number of values if the corresponding bit of the expansion control information is 1.

A processor comprising:

• a scalar processor core;
• and
• a vector coprocessor core coupled to the scalar processor core;
• the vector coprocessor core configured to execute vector instructions passed by the scalar processor core, the vector coprocessor core comprising:
• a plurality of execution units arranged to execute an instruction in parallel;
• a register file, comprising a plurality of registers coupled to the execution units;
• a plurality of load units, at least one of the load units configured to move a predetermined number of values in adjacent memory locations to adjacent registers as controlled by expansion control information, the expansion control information having a number of bits equal to the number of registers, with a number of 1 bits equal to the predetermined number of values, a register storing all 0s if a corresponding bit of the expansion control information 0 and a next of the predetermined number of values if the corresponding bit of the expansion control information is 1;
• and
• a plurality of store units, at least one of the store units configured to move values in adjacent registers to a predetermined number of adjacent memory locations as controlled by collation control information, the collation control information having a number of bits equal to the number of adjacent registers, with a number of 1 bits equal to the predetermined number of values, a memory storing a value stored in a next adjacent register having corresponding bit of the collation control information of 1.