Serial bus buffer with noise reduction

A serial bus buffer comprising:

• a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
• a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device;
• and
• a controller coupled between the primary interface and the buffered interface and configured to:
• receive a first data signal and a clock signal at the primary interface;
• select a first drive level from one of a first plurality of available drive levels;
• and
• replicate the first data signal and the clock signal at the first drive level at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface.

A serial bus buffer comprising:

• a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
• a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device;
• and
• a controller coupled between the primary interface and the buffered interface and configured to:
• receive a first data signal and a clock signal at the primary interface;
• replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute a first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface;
• receive a second data signal at the buffered interface;
• and
• replicate the second data signal at the primary interface upon receiving a second command within the second data signal to execute a second mode that passes the second data signal and the clock signal from the buffer interface to the primary interface.

A serial bus buffer comprising:

• a primary interface coupled to a primary serial data line and a primary serial clock line of a primary bus, wherein the primary bus is coupled to a first device and at least one second device;
• a buffered interface coupled to a buffered serial data line and a buffered serial clock line of a buffered bus, wherein the buffered bus is coupled to at least one third device;
• and
• a controller coupled between the primary interface and the buffered interface and to:
• receive a first data signal and a clock signal at the primary interface;
• during a first mode, replicate the first data signal and the clock signal at the buffered interface upon receiving a first command within the first data signal to execute the first mode that passes the first data signal and the clock signal from the primary interface to the buffered interface;
• and
• during a second mode, the first data signal and the clock signal are not replicated at the buffered interface upon receiving a second command within the first data signal to execute the second mode that blocks the passing of the first data signal and the clock signal from the primary interface to the buffered interface.