Interconnection network topology for large scale high performance computing (HPC) systems

Abstract

A multiprocessor computer system includes a plurality of processor nodes and at least a three-tier hierarchical network interconnecting the processor nodes. The hierarchical network includes a plurality of routers interconnected such that each router is connected to a subset of the plurality of processor nodes; the plurality of routers are arranged in a hierarchy of n≧3 tiers (T1, . . . , Tn); the plurality of routers are partitioned into disjoint groups at the first tier T1, the groups at tier Ti being partitioned into disjoint groups (of complete Ti groups) at the next tier Ti+1 and a top tier Tn including a single group containing all of the plurality of routers; and for all tiers 1≦i≦n, each tier-Ti−1 subgroup within a tier Ti group is connected by at least one link to all other tier-Ti−1 subgroups within the same tier Ti group.

Dependencies are inferred from the claim text.