Systems and methods for frequency control on a bus through superposition
AssigneeQUALCOMM Incorporated
InventorTimothy Mowry Hollis
Life of this patent
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Abstract
Systems and methods for frequency control on a bus through superposition are disclosed. In one embodiment, instead of adding pins or increasing the operating frequency of the bus, three signals are placed on lines within the bus using superposition. In this fashion, three bits may be sent over two conductors, effectively obviating the need for an additional pin and effectively increasing the frequency of bit transmission without having to increase the clock speed.
Claims26
A method for conveying data across a bus, comprising:
- parsing a data signal into a plurality of bits;
- identifying a first bit of the plurality of bits for transmission on a first conductor of the bus through a first pin;
- identifying a second bit of the plurality of bits for transmission on a second conductor of the bus through a second pin;
- steering a third bit of the plurality of bits onto the first bit or the second bit based on the value of the third bit;
- combining the third bit with the first bit or second bit based on the steering and sending a combined bit to one of the first conductor and second conductor based on which bit was combined;
- and
- sending the first, second, and third bits to the bus through the first and second pins.
A transmitter within an integrated circuit configured to send signals across a data bus, the transmitter comprising:
- a first bit source configured to generate a first bit, the first bit source coupled to a first external pin on the integrated circuit;
- a second bit source configured to generate a second bit, the second bit source coupled to a second external pin on the integrated circuit;
- a third bit source configured to generate a third bit;
- a control system configured to:
- parse a data signal into a plurality of bits;
- identify the first bit within the plurality of bits for transmission on a first conductor of the data bus through the first external pin;
- and
- identify the second bit within the plurality of bits for transmission on a second conductor of the data bus through the second external pin;
- and
- a switch assembly associated with the third bit source and configured to switch the third bit source between the first external pin and the second external pin based on steering from the control system.
A data transmission system comprising:
- a two wire data bus;
- a transmitter within an integrated circuit, the transmitter comprising:
- a first bit source configured to generate a first bit, the first bit source coupled to a first external pin on the integrated circuit, the first external pin coupled to a first wire of the two wire data bus;
- a second bit source configured to generate a second bit, the second bit source coupled to a second external pin on the integrated circuit, the second external pin coupled to a second wire of the two wire data bus;
- a third bit source configured to generate a third bit;
- a control system configured to:
- parse a data signal into a plurality of bits;
- identify the first bit within the plurality of bits for transmission on the first wire of the two wire data bus through the first external pin;
- and
- identify the second bit within the plurality of bits for transmission on the second wire of the two wire data bus through the second external pin;
- and
- a switch assembly associated with the third bit source and configured to switch the third bit source between the first external pin and the second external pin based on steering from the control system.
Dependencies are inferred from the claim text.