Method and apparatus to enable multiple masters to operate in a single master bus architecture
AssigneeQUALCOMM Incorporated
InventorsShoichiro Sengoku, Richard Dominic Wietfeldt, George Alan Wiley
Life of this patent
Estimating the term…
Loading patent…
AssigneeQUALCOMM Incorporated
InventorsShoichiro Sengoku, Richard Dominic Wietfeldt, George Alan Wiley
Estimating the term…
To accommodate multiple masters over bus architectures supporting a single master device, a mechanism is provided for an inactive master device to trigger an IRQ signal over a shared, single line IRQ bus. A current master then polls the other inactive master devices over a shared data bus to ascertain which inactive master device is asserting the IRQ signal. Upon identifying the asserting inactive master device, the current master device grants control of the data bus to the new master device, thereby making the inactive master the new active master device.
A device, comprising:
A method operational on a device, comprising:
A non-transitory machine-readable storage medium having one or more instructions stored thereon, which when executed by at least one processor causes the at least one processor to:
A device, comprising:
Dependencies are inferred from the claim text.