Back to results
US 9,519,546 B2Granted
Striping cache blocks with logical block address scrambling
AssigneeDell Products L.P.
InventorsScott Peterson, Phillip Krueger
Life of this patent
Estimating the term…
Abstract
A method for information handling systems includes receiving a storage operation to be applied to a cache block in a location in a distributed storage system. The location is defined by a logical block address (LBA). The method further includes swapping a first portion of the LBA with a second portion of the LBA, resulting in a modified LBA, and performing the storage operation with the modified LBA. The first portion and the second portion are both x bits wide.
Claims26
A method for information handling systems, comprising:
- receiving a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
- swapping a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA;
- and
- performing the storage operation with the modified LBA.
1 more element
An article of manufacture, comprising:
- a non-transitory machine-readable medium;
- and
- instructions on the computer-readable medium, when read by a processor, are configured to cause the processor to:
- receive a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
- swap a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA;
- and
- perform the storage operation with the modified LBA.
4 more elements
An information handling system, comprising:
- a processor;
- a machine-readable medium comprising instructions, when read and executed by the processor, are configured to cause the processor to:
- receive a storage operation to be applied to a cache block in a location in a distributed storage system, the location defined by a logical block address (LBA);
- swap a first portion of the LBA that includes the highest x bits of an offset definition with a second portion of the LBA, wherein the first portion and the second portion are both x bits wide, resulting in a modified LBA;
- and
- perform the storage operation with the modified LBA.
3 more elements
Dependencies are inferred from the claim text.