Apparatus, system, and method for destaging cached data

An apparatus for satisfying storage requests while destaging cached data, the apparatus comprising:

• a monitor module that samples a destage rate for a nonvolatile solid-state cache, a total cache write rate for the cache, and a dirtied data rate, the destage rate comprising a rate at which dirty data is destaged from the cache, the total cache write rate comprising a total amount of data written to the cache in response to user write requests, the total cache write rate further comprising a dirty write hit rate and a clean write hit rate, the dirty write hit rate comprising a rate at which cache writes invalidate dirty data in the cache, the clean write hit rate comprising a rate at which cache writes invalidate previously destaged clean data in the cache, the dirtied data rate comprising a rate at which write operations increase an amount of dirty data in the cache;
• a target module that determines a target cache write rate for the cache based on the destage rate, the total cache write rate, and the dirtied data rate to target a destage write ratio, the destage write ratio comprising a predetermined ratio between the dirtied data rate and the destage rate;
• and
• a rate enforcement module that enforces the target cache write rate such that the total cache write rate satisfies the target cache write rate.

A system for satisfying storage requests while destaging cached data, the system comprising:

• a nonvolatile solid-state cache;
• a backing store for the nonvolatile solid-state cache;
• a cache controller for the nonvolatile solid-state cache, the cache controller comprising,
• a monitor module that samples a destage rate from the cache to the backing store, a total cache write rate for the cache, and a dirtied data rate, the destage rate comprising a rate at which dirty data is destaged from the cache, the total cache write rate comprising a total amount of data written to the cache in response to user write requests, the total cache write rate further comprising a dirty write hit rate and a clean write hit rate, the dirty write hit rate comprising a rate at which cache writes invalidate dirty data in the cache, the clean write hit rate comprising a rate at which cache writes invalidate previously destaged clean data in the cache, the dirtied data rate comprising a rate at which write operations increase an amount of dirty data in the cache;
• a target module that determines a target cache write rate for the cache based on the destage rate, the total cache write rate, and the dirtied data rate to target a destage write ratio, the destage write ratio comprising a predetermined ratio between the dirtied data rate and the destage rate;
• and
• a rate enforcement module that enforces the target cache write rate such that the total cache write rate satisfies the target cache write rate.