Handling system interrupts with long-running recovery actions
AssigneeLenovo Enterprise Solutions (Singapore) Pte. Ltd.
InventorsJonathan L. Kaus, Adam C. Lange-Pearson, Gary R. Ricard, Jaimeson Saley
Life of this patent
Estimating the term…
Abstract
A method, processor, and computer system for handling interrupts within a hierarchical register structure. The method includes receiving at a root-level register an indication of an interrupt occurring at a lower level register in the register structure, using a system interrupt handler to invoke an error handler assigned to a set of registers of the structure that includes the lower level register, and using the invoked error handler to handle the interrupt and return to the system interrupt handler.
Claims20
A processor, comprising:
- a hierarchical interrupt register structure, comprising:
- a plurality of lower level registers, and
- a first root-level register configured to indicate an interrupt occurring at a first lower level register of the plurality of lower level registers;
- one or more error handlers, each error handler of the one or more error handlers assigned to a respective set of registers of the interrupt register structure;
- and
- a system interrupt handler configured to determine, based on a determined amount of time required to complete a prescribed recovery action for an interrupt, whether to directly handle the interrupt or to invoke an error handler of the one or more error handlers to handle the interrupt.
A computer system, comprising:
- a processor, comprising:
- a hierarchical interrupt register structure, comprising:
- a plurality of lower level registers, and
- a first root-level register configured to indicate an interrupt occurring at a first lower level register of the plurality of lower level registers;
- one or more error handlers, each error handler of the one or more error handlers assigned to a respective set of registers of the interrupt register structure;
- and
- a system interrupt handler configured to determine, based on a determined amount of time required to complete a prescribed recovery action for an interrupt, whether to directly handle the interrupt or to invoke an error handler of the one or more error handlers to handle the interrupt.
A method of handling interrupts in a processor comprising a hierarchical interrupt register structure, the method comprising:
- receiving, at a root-level register of the interrupt register structure, an indication of an interrupt occurring at a lower level register of the interrupt register structure;
- determining, at a system interrupt handler and based on a determined amount of time required to complete a prescribed recovery action for the interrupt, whether to directly handle the interrupt with the system interrupt handler or to invoke an error handler to handle the interrupt;
- and
- handling the interrupt based on the determination.
Dependencies are inferred from the claim text.