Executing an instruction of currently active thread before context switch upon receiving inactive context ID to be activated
AssigneeARM Finance Overseas Limited
InventorsRobert Gelinas, W. Patrick Hays, Sol Katzman, William J. Dally
Life of this patent
Estimating the term…
Abstract
Systems and methods for managing context switches among threads in a processing system. A processor may perform a context switch between threads using separate context registers. A context switch allows a processor to switch from processing a thread that is waiting for data to one that is ready for additional processing. The processor includes control registers with entries which may indicate that an associated context is waiting for data from an external source.
Claims12
A method for context switching in an electronic processor, comprising:
- receiving, at the electronic processor from a scheduler, an identity of a first context, the first context currently inactive;
- performing, at the electronic processor after the receiving the identity of the first context, a first instruction of a thread associated with a second context, the second context currently active;
- storing, at the electronic processor at a context program counter register of the second context, a program counter of the first instruction;
- and
- pointing, at the electronic processor, a processor program counter to a context program counter register of the first context.
A system for context switching, comprising:
- a memory configured to store an identity of a first context, the first context currently inactive;
- and
- an electronic processor having a context program counter register of the first context, a context program counter register of a second context, and a processor program counter, the electronic processor configured to perform, after the identity of the first context is stored in the memory, a first instruction of a thread associated with the second context, the second context currently active, the electronic processor configured to store, at the context program counter register of the second context, a program counter of the first instruction, and the electronic processor configured to point the processor program counter to the context program counter register of the first context.
Dependencies are inferred from the claim text.