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US 9,519,488 B2Granted
External intrinsic interface
AssigneeSamsung Electronics Co., Ltd.
InventorsKwon Taek Kwon, Seok Yoon Jung
Life of this patent
Estimating the term…
Abstract
An external intrinsic interface. A processor may include a core including a plurality of functional units, an intrinsic module located outside the core, and an interface module to perform relaying between the intrinsic module and a functional unit, among the plurality of functional units.
Claims19
A processor, comprising:
- a core comprising of functional units;
- an intrinsic module disposed outside the core;
- and
- an interface module to perform relaying between the intrinsic module and a functional unit among the functional units, such that stall cycle hiding is performed in response to a stall occurring in the core or the intrinsic module, and wherein whether the stall cycle hiding is performed by an output FIFO register or an input FIFO register is determined by which one of the core or the intrinsic module the stall occurs in, wherein in response to a stall occurring in the core, the interface module stalls the intrinsic module based on an available storage space in an output FIFO register, and wherein in response to a stall occurring in the intrinsic module, a control unit of the interface module stalls the core based on an available storage space in an input FIFO register.
1 more element
A processor, comprising:
- a core comprising functional units;
- and
- an intrinsic module disposed outside the core and processing operation requests for the functional units, the processor being operated such that stall cycle hiding is performed in response to a stall occurring in the core or the intrinsic module, and wherein whether the stall cycle hiding is performed by an output FIFO register or an input FIFO register is determined by which one of the core or the intrinsic module the stall occurs in, wherein in response to a stall occurring in the core, a control unit stalls the intrinsic module based on an available storage space in an output FIFO register, and wherein in response to a stall occurring in the intrinsic module, the control unit stalls the core based on an available storage space in an input FIFO register.
Dependencies are inferred from the claim text.