US 9,519,483 B2Granted

Generating flags for shifting and rotation operations in a processor

AssigneeAdvanced Micro Devices, Inc.

InventorsSrikanth Arekapudi, Saurabh Gupta

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Abstract

A method and apparatus are described for generating flags in response to processing data during an execution pipeline cycle of a processor. The processor may include a multiplexer configured to generate valid bits for received data according to a designated data size, and a logic unit configured to control the generation of flags based on a shift or rotate operation command, the designated data size and information indicating how many bytes and bits to rotate or shift the data by. A carry flag may be used to extend the amount of bits supported by shift and rotate operations. A sign flag may be used to indicate whether a result is a positive or negative number. An overflow flag may be used to indicate that a data overflow exists, whereby there are not a sufficient number of bits to store the data.

Claims18

Dependent claims

A method of generating flags in response to processing data during an execution pipeline cycle of a processor, the method comprising:

generating valid bits for received data comprising a plurality of bits according to a received designated data size indicating how many of the plurality of bits of the received data comprise the valid bits;
receiving a shift or rotate operation command;
receiving information indicating how many bytes and bits to rotate the received data or shift the received data;
generating rotated data using:
the valid bits;
the shift operation command or rotate operation command;
and the information;
replacing one or more of the valid bits shifted out of the received data with one or more replacement bits comprising one of:
(i) one or more most significant bits (MSBs) of the valid bits;
and (ii) one or more logic zero bits;
generate a rotate-shift result by selecting between the one or more replacement bits and the rotated data;
comparing (i) the received designated data size indicating how many of the plurality of bits of received data comprise the valid bits to (ii) the received information indicating how many bytes and bits to rotate the received data or shift the received data;
and
controlling generation of a carry flag, an overflow flag, and a sign flag by selecting between a plurality of carry flag selections, a plurality of overflow flag selections, and a plurality of sign flag selections based on the received shift operation command or rotate operation command and the comparison of the received designated data size indicating how many of the plurality of bits of received data comprise the valid bits to the received information indicating how many bytes and bits to rotate the received data or shift the received data,
wherein the carry flag, the overflow flag, and the sign flag are generated within a single cycle of the generating of the rotate-shift result.

12 more elements

A non-transitory computer-readable storage medium comprising a set of instructions used for manufacturing a semiconductor device, wherein the semiconductor device comprises:

an input multiplexer configured to generate valid bits for source data comprising a plurality of bits according to a designated data size, the designated data size indicating how many of the plurality of bits of the source data comprise the valid bits;
a rotator array configured to generate rotated data using:
the valid bits;
a shift or a rotate operation command;
and information indicating how many bytes and bits to rotate or shift the source data;
an output multiplexor configured to:
replace one or more of the valid bits shifted out of the source data with one or more replacement bits comprising one of:
(i) one or more most significant bits (MSBs) of the valid bits;
and (ii) one or more logic zero bits;
generate a rotate-shift result by selecting between the one or more replacement bits and the rotated data;
a logic unit configured to:
compare (i) the designated data size to (ii) the information indicating how many bytes and bits to rotate the source data or shift the source data;
and
control generation of a carry flag, an overflow flag, and a sign flag by selecting between a plurality of carry flag selections, a plurality of overflow flag selections, and a plurality of sign flag selections based on the shift or rotate operation command and the comparison of (i) the designated data size to (ii) the information indicating how many bytes and bits to rotate the data or shift the data,
wherein the designated data size, the shift or rotate operation command and the information indicating how many bytes and bits to rotate the source data or shift the source data are each provided in parallel to the output multiplexor and the logic unit.

12 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/334,286Filed 22 Dec 2011
Published: US 2013/0166889 A127 Jun 2013
Granted: 13 Dec 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification3 codes

G06F 9/30094
Arrangements for executing machine instructions, e.g. instruction decode: condition code generation, e.g. Carry, Zero flag
G06F 9/30032
To perform operations on data operands: movement instructions, e.g. move, shift, rotate, shuffle
G06F
Computing and data processing

Family

US 2013/0166889 A1Pre-grant publication · published 27 Jun 2013
US 9,519,483 B2This patent

From the US filing history. Foreign family members aren’t listed.

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