Techniques for increasing vector processing utilization and efficiency through vector lane predication prediction

A method of vector lane predication for a processor, comprising the steps of:

• fetching predicated vector instructions from a memory;
• decoding the predicated vector instructions;
• determining if a mask value of the predicated vector instructions is available and, if the mask value of the predicated vector instructions is not available, predicting the mask value of the predicated vector instructions;
• dispatching the predicated vector instructions to only masked vector lanes;
• dispatching non-conflicting instructions to only unmasked vector lanes at a same time as the predicated vector instructions are dispatched to the masked vector lanes;
• issuing the predicated vector instructions to functional units of the processor;
• executing the predicated vector instructions with the functional units of the processor;
• writing back data resulting from executing the predicated vector instructions for all vector lanes including the masked and unmasked vector lanes to a register file, wherein
• the mask value of the predicated vector instructions is predicted, the method further comprising the step of determining whether the mask value of the predicated vector instructions that is predicted is correct and, if the mask value of the predicated vector instructions that is predicted is incorrect, removing the predicated vector instructions for which the mask value that is predicted is incorrect, and resuming the method at the fetching step;
• decrementing a safeguard counter each time it is determined that the mask value of the predicated vector instructions that is predicted is incorrect, wherein the safeguard counter is set at a dynamic maximum tolerance level that includes a maximum bound of incorrect predictions that will be tolerated by taking into account a performance improvement of the processor device by the correct prediction of the mask value and also taking into account a performance penalty of the processor device by the incorrect prediction of the mask value;
• and
• reverting to a baseline process when the safeguard counter reaches zero which dispatches a same predicated vector instruction to all lanes until the mask value is known.

An apparatus for vector lane predication, the apparatus comprising:

• a memory;
• and
• at least one processor device, coupled to the memory, operative to:
• fetch predicated vector instructions from the memory;
• decode the predicated vector instructions;
• determine if a mask value of the predicated vector instructions is available and, if the mask value of the predicated vector instructions is not available, predicting the mask value of the predicated vector instructions;
• dispatch the predicated vector instructions to only masked vector lanes;
• and
• dispatch non-conflicting instructions to only unmasked vector lanes at a same time as the predicated vector instructions are dispatched to the masked vector lanes, wherein
• the mask value of the predicated vector instructions is predicted, the at least one processor device is further operative to determine whether the mask value of the predicated vector instructions that is predicted is correct and, if the mask value of the predicated vector instructions that is predicted is incorrect, removing the predicated vector instructions for which the mask value that is predicted is incorrect, resume the fetch predicated vector instructions from the memory;
• decrement a safeguard counter each time it is determined that the mask value of the predicated vector instructions that is predicted is incorrect, wherein the safeguard counter is set at a dynamic maximum tolerance level that includes a maximum bound of incorrect predictions that will be tolerated by taking into account a performance improvement of the processor device by the correct prediction of the mask value and also taking into account a performance penalty of the processor device by the incorrect prediction of the mask value;
• and
• revert to a baseline process when the safeguard counter reaches zero which dispatches a same predicated vector instruction to all lanes until the mask value is known.

A non-transitory article of manufacture for vector lane predication for a processor, comprising a machine-readable recordable medium containing one or more programs which when executed implement the steps of:

• fetching predicated vector instructions from a memory;
• decoding the predicated vector instructions;
• determining if a mask value of the instructions is available and, if the mask value of the predicated vector instructions is not available, predicting the mask value of the predicated vector instructions;
• dispatching the predicated vector instructions to only masked vector lanes;
• dispatching non-conflicting instructions to only unmasked vector lanes at a same time as the predicated vector instructions are dispatched to the masked vector lanes;
• decrementing a safeguard counter each time it is determined that the mask value of the predicated vector instructions that is predicted is incorrect, wherein the safeguard counter is set at a dynamic maximum tolerance level that includes a maximum bound of incorrect predictions that will be tolerated by taking into account a performance improvement of the processor device by the correct prediction of the mask value and also taking into account a performance penalty of the processor device by the incorrect prediction of the mask value;
• reverting to a baseline process when the safeguard counter reaches zero which dispatches a same predicated vector instruction to all lanes until the mask value is known;
• and
• resetting the safeguard counter after a preset period of time to permit re-execution of the method for a different phase of a workload.