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AssigneeCadence Design Systems, Inc.
InventorsAamir A. Farooqui, David Lawrence Heine
Estimating the term…
A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus and method. A multiplier block with two 16-bit by 32-bit multiplier circuits transform a selectable number of input multipliers and multiplicands into a selected number of products. Each multiplier circuit comprises an array of full adders that generates and sums partial products using carry-save addition. An accumulator block, with additional data width to help prevent overflow, adds the products to a selectable number of input addends and outputs a number of results. Embodiments perform one to four multiplications together, depending on the number of bits (eight, 16, 24, or 32) selected for the input operands. Embodiments output 20-bit, 40-bit, or 80-bit multiply-accumulate results at rates of at least 1.1 GHz. Embodiments support signed inputs, negated multiplication products, and Q-format data. A hybrid sign extension management approach improves performance for 80-bit outputs.
A single-instruction multiple-data (SIMD) multiplier-accumulator apparatus comprising:
A method for performing single-instruction multiple-data (SIMD) multiply-accumulate data processing operations with a SIMD multiplier-accumulator apparatus, comprising:
A non-transitory computer readable medium storing instructions that, when executed by a processor, perform a method for single-instruction multiple-data (SIMD) multiply-accumulate data processing operations comprising:
Dependencies are inferred from the claim text.