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US 9,519,459 B2Granted
High efficiency computer floating point multiplier unit
AssigneeWisconsin Alumni Research Foundation
InventorsNam Sung Kim, Syed Gilani, Michael Schulte
Life of this patent
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Abstract
A high-power-efficiency multiplier combines a standard floating-point multiplier with a power-of-two multiplier that performs multiplications by shifting operations without the need for floating-point multiplication circuitry. By selectively steering some operands to this power-of-two multiplier, substantial power savings may be realized. In one embodiment, multiplicands may be modified to work with the power-of-two multiplier introducing low errors that may be accommodated in pixel calculations.
Claims18
A multiplier circuit system for multiplying floating-point numbers expressed as exponents and significands in an electronic computer comprising:
- a floating-point multiplier circuit receiving floating-point multiplicands having a first significand length and outputting a floating-point product of the floating-point multiplicands;
- a power-of-two multiplier circuit receiving at least one constrained floating-point multiplicand having a second significand length less than the first significand length and outputting a floating-point product only for a product including at least one constrained floating-point multiplicand;
- and
- a selector circuit directing floating-point multiplicands including at least one constrained floating-point multiplicand to the power-of-two multiplier circuit and directing a floating-point multiplicand not including at least one constrained floating-point multiplicand to the floating-point multiplier circuit and outputting a floating-point from a corresponding one of the power-of-two multiplier circuit and floating-point multiplier circuit;
- wherein the selector circuit receives floating-point multiplicands and modifies at least some floating-point multiplicands to be constrained floating-point multiplicands when the modification changes the value of the received floating-point multiplicands by less than a predetermined error value and directs the modified floating-point multiplicands to the power-of-two multiplier circuit as constrained floating-point multiplicands.
2 more elements
A multiplier circuit system for multiplying floating-point numbers expressed as exponents and significands in an electronic computer comprising:
- a floating-point multiplier circuit receiving floating-point multiplicands having a first significand length and outputting a floating-point product of the floating-point multiplicands:
- a power-of-two multiplier circuit receiving at least one constrained floating-point multiplicand having a second significand length less than the first significand length and outputting a floating-point product only for a product including at least one constrained floating-point multiplicand;
- and
- a selector circuit directing floating-point multiplicands including at least one constrained floating-point multiplicand to the power-of-two multiplier circuit and directing a floating-point multiplicand not including at least one constrained floating-point multiplicand to the floating-point multiplier circuit and outputting a floating-point from a corresponding one of the power-of-two multiplier circuit and floating-point multiplier circuit;
- wherein the power-of-two multiplier circuit further includes a significand shifter shifting one multiplicand if the multiplicand is a sum of two numbers equal to powers-of-two.
2 more elements
A method of multiplying digital values employing a multiplier circuit system for an electronic computer having:
- a floating-point multiplier circuit receiving floating-point multiplicands and outputting a floating-point product of the floating-point multiplicands;
- a power-of-two multiplier circuit receiving constrained floating-point multiplicands and outputting a floating-point product of the constrained floating-point multiplicands when the constrained floating-point multiplicands include at least one multiplicand limited to a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two;
- and
- a selector circuit directing floating-point multiplicands received by the multiplier circuit system to one of the floating-point multiplier circuit and power-of-two multiplier circuit and directing a corresponding one of the floating-point products of the floating-point multiplier circuit and power-of-two multiplier circuit to an output from the multiplier circuit system, the method comprising the steps of:
- (a) evaluating by the multiplier circuit the multiplicands to determine when at least one multiplicand is a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two;
- (b) when at least one multiplicand is a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two, causing the selector circuit to direct both multiplications to the power-of-two multiplier;
- and
- (c) multiplying multiplicands directed to the power-of-two multiplier by the power-of-two multiplier;
- further including the step of causing the selector circuit to direct both multiplicands to the power-of-two multiplier when at least one multiplicand may be approximated by a number equal to an integer power-of-two or a sum of two numbers each equal to an integer power-of-two to within a predetermined error magnitude.
6 more elements
Dependencies are inferred from the claim text.