Method for concurrent system management and error detection and correction requests in integrated circuits through location aware avoidance logic

A concurrent system management method for a memory system, the method comprising:

• providing a memory comprising a plurality of memory cells, wherein each memory cell comprises one or more access ports, and wherein the memory cells are arranged into banks;
• providing a command arbitration unit coupled to the memory to enable concurrent processing of multiple internally and externally generated commands;
• providing an input clock for the memory system;
• queuing multiple internally generated memory commands using the command arbitration unit;
• issuing an externally generated command;
• defining memory array access priorities internally using an on-chip algorithm that is not affected by the externally generated memory commands;
• issuing a highest priority request;
• concurrently issuing lower priority requests to a memory interface with the highest priority request;
• receiving an input clock event;
• all commands issued by the command arbitration unit are processed by the bank associated with each request;
• and
• the command arbitration unit preserves unprocessed lower priority commands for a future input clock event.