US 9,519,428 B2Granted

Dynamically improving performance of a host memory controller and a memory device

AssigneeQUALCOMM Incorporated

InventorsNir Strauss, David Teb, Racheli Angel Manor

Life of this patent

Estimating the term…

Loading patent…

Abstract

Methods, apparatuses, systems, and computer-readable media for dynamically improving performance of a host memory controller and a hosted memory device are presented. According to one or more aspects, a memory controller may establish a data connection with a memory device. The memory controller may perform a first write operation of a plurality of write operations to the memory device using a first block size. Subsequently, the memory controller may perform a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size. The memory controller then may determine an optimal value for a block size parameter based at least in part on the plurality of write operations. Thereafter, the memory controller may use the optimal value for the block size parameter in performing one or more regular tasks involving the memory device.

Claims36

Dependent claims

A method comprising:

establishing, by a memory controller, a data connection with a memory device, the memory device adhering to a common standard as the memory controller;
determining, by the memory controller, whether the memory device is recognized or not and, upon determining that the memory device is not recognized:
(i) performing, by the memory controller, a first write operation of a plurality of write operations to the memory device using a first block size;
(ii) performing, by the memory controller, a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size, wherein the first block size and the second block size are included in a sweep pattern of different block sizes, the sweep pattern determined based on at least one of:
(a) the standard or (b) one or more modes of the standard;
(iii) determining, by the memory controller, an optimal value for a block size parameter associated with the memory device based at least in part on the plurality of write operations;
and
(iv) storing, by the memory controller, the optimal value for the block size parameter associated with the memory device, the stored optimal value associated with the memory device retrievable upon recognition of the memory device;
and
using, by the memory controller, a stored optimal value for a block size parameter associated with the memory device in performing one or more regular tasks involving the memory device,
wherein a first optimal value is determined for a first mode of operation defined by the standard, and
wherein a second optimal value is determined for a second mode of operation defined by the standard, the second mode being different from the first mode.

9 more elements

At least one non-transitory computer-readable medium having computer-executable instructions stored thereon that, when executed, cause at least one computing device to:

establish a data connection with a memory device, the memory device adhering to a common standard as the at least one computing device;
determine whether the memory device is recognized or not and upon determining that the memory device is not recognized:
(i) perform a first write operation of a plurality of write operations to the memory device using a first block size;
(ii) perform a second write operation of the plurality of write operations to the memory device using a second block size different from the first block size, wherein the first block size and the second block size are included in a sweep pattern of different block sizes, the sweep pattern determined based on at least one of:
(a) the standard or (b) one or more modes of the standard;
(iii) determine an optimal value for a block size parameter associated with the memory device based at least in part on the plurality of write operations;
and
(iv) store the optimal value for the block size parameter associated with the memory device, the stored optimal value associated with the memory device retrievable upon recognition of the memory device;
and
use a stored optimal value for a block size parameter associated with the memory device in performing one or more regular tasks involving the memory device,
wherein a first optimal value is determined for a first mode of operation defined by the standard, and
wherein a second optimal value is determined for a second mode of operation defined by the standard, the second mode being different from the first mode.

9 more elements

An apparatus, comprising:

at least one processor;
a memory controller;
and
memory storing computer-readable instructions that, when executed by the at least one processor, cause the apparatus to:
establish, via the memory controller, a data connection with a memory device, the memory device adhering to a common standard as the memory controller;
determine whether the memory device is recognized or not and upon determining that the memory device is not recognized:
(i) perform a first write operation of a plurality of write operations to the memory device using a first block size;
(ii) perform a second write operation of the plurality of write operations to the memory device using a second block size, wherein the first block size and the second block size are included in a sweep pattern of different block sizes, the sweep pattern determined based on at least one of:
(a) the standard or (b) one or more modes of the standard;
(iii) determine an optimal value for a block size parameter associated with the memory device based at least in part on the plurality of write operations;
and
(iv) store the optimal value for the block size parameter associated with the memory device, the stored optimal value associated with the memory device retrievable upon recognition of the memory device;
and
use a stored optimal value for a block size parameter associated with the memory device in performing one or more regular tasks involving the memory device,
wherein a first optimal value is determined for a first mode of operation defined by the standard, and
wherein a second optimal value is determined for a second mode of operation defined by the standard, the second mode being different from the first mode.

13 more elements

A system comprising:

means for establishing a data connection with a memory device, the memory device adhering to a common standard as a memory controller;
means for determining whether the memory device is recognized or not and upon determining that the memory device is not recognized:
(i) means for performing a first write operation of a plurality of write operations to the memory device using a first block size;
(ii) means for performing a second write operation of the plurality of write operations to the memory device using a second block size, wherein the first block size and the second block size are included in a sweep pattern of different block sizes, the sweep pattern determined based on at least one of:
(a) the standard or (b) one or more modes of the standard;
(iii) means for determining an optimal value for a block size parameter associated with the memory device based at least in part on the plurality of write operations;
and
(iv) means for storing the optimal value for the block size parameter associated with the memory device, the stored optimal value associated with the memory device retrievable upon recognition of the memory device;
and
means for using a stored optimal value for a block size parameter associated with the memory device in performing one or more regular tasks involving the memory device,
wherein a first optimal value is determined for a first mode of operation defined by the standard, and
wherein a second optimal value is determined for a second mode of operation defined by the standard, the second mode being different from the first mode.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application: 13/628,006Filed 26 Sep 2012
Published: US 2014/0089610 A127 Mar 2014
Granted: 13 Dec 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 3/061
Specifically adapted to achieve a particular effect: improving I/O performance
G06F 3/0634
Configuration or reconfiguration of storage systems: by changing the state or mode of one or more devices
G06F 3/064
Organizing or formatting or addressing of data: management of blocks
G06F 3/0659
Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices: command handling…

Family

US 2014/0089610 A1Pre-grant publication · published 27 Mar 2014
US 9,519,428 B2This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key