Liquid crystal display device with touch panel

A display device with a touch panel comprising:

• a plurality of scanning signal lines, which are aligned in a rectangular display region and in parallel with a side of the rectangular display region, to which an active potential as a potential for making a pixel transistor conductive is applied;
• at least one drive pulse output circuit which sequentially applies the active potential to the plurality of scanning signal lines in the display region;
• a clock signal output circuit which applies a first clock signal as a clock signal for the drive pulse output circuits to a first clock signal line and stops the application of the first clock signal to the first clock signal line for a stop period during which the sequential application of the active potential to the plurality of scanning signal lines is stopped in the middle thereof;
• a touch panel control unit which detects contact with a display surface during the stop period;
• and
• at least one reset start signal generation circuit which includes a transfer circuit block, a reset circuit block and a start circuit block, and generates and outputs a reset signal for resetting the finally applied active potential to a non-active potential when the sequential application of the active potential by the drive pulse output circuit is stopped in the middle and a start signal for restarting the stopped sequential application of the active potential from the middle,
• wherein the transfer circuit block includes a circuit to be used by the respective circuit blocks in the reset start signal generation circuit to output a transfer signal,
• wherein the reset circuit block includes the circuit of the transfer circuit block, and generates and outputs the reset signal,
• wherein the start circuit block includes the circuit of the transfer circuit block, and generates and outputs the start signal,
• wherein the clock signal output circuit supplies a second clock signal, which is a clock signal with a lower frequency than that of the first clock signal, to the reset start signal generation circuit, and
• wherein the respective circuit blocks in the reset start signal generation circuit are operated based on the second clock.